Martin Roth wrote: > 2) The microcode that's included for the intel FSP is for B2/B3 silicon, > but it seems like many users are still using B0 silicon, which requires a > different microcode patch. This shouldn't be a problem but since there are > 4 SKUs of Bay Trail and using the microcode for the wrong SKU will *APPEAR* > to work, but cause issues later
Are you saying that there is no way for coreboot to know which silicon it is running on? If the same code is supposed to work across more silicon revisions then the only helpful solution I can think of is to allow choosing in Kconfig which platforms should be supported by the image that is being built. Yes/no per silicon revision, with microcode pulled in for each one. The code would need to check at runtime which silicon it is running on, and load the corresponding microcode. //Peter -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
