If your platform still does not boot up, I would suggest you check the SoC revision on your platform with the microcode revision of your coreboot, these two revisions should be matched, if not, system will halt in a every early stage.
Another possibility you should consider is that if the UART configuration of your board, if it's wrong, you definitely will not have any output on serial console. On Thu, Feb 4, 2016 at 2:02 PM, WANG FEI <[email protected]> wrote: > *RANGELEY_POSTGOLD4_FSP_004_20150924.fd is the FSP binary, you can rename > it to FvFsp.bin and placed it to the path defined in coreboot, ie, * > `../intel/fsp/rangeley/Fv*, to generate coreboot image.* > > On Thu, Feb 4, 2016 at 5:19 AM, 김유석 <[email protected]> wrote: > >> Dear Martin. >> >> Thank's your advise. >> >> I'm use the serial consol port. but can't see any message. >> >> Thank you. >> >> 2016-02-02 오후 9:18에 Martin Roth 이(가) 쓴 글: >> >> You might try a different video card. There's an issue in the video bios >> of the aspeed card that came with the mohon peak. >> >> martin >> On Tue, Feb 2, 2016 at 00:41 김유석 < <[email protected]> >> [email protected]> wrote: >> >>> Dear sir. >>> >>> My ENV is see below. >>> >>> *EVB : Intel rangeley Mohon Peak CRB* >>> >>> >>> This time, I was download the coreboot from git. >>> >>> poplinux@raw work $ > git clone >>> <http://review.coreboot.org/coreboot.git> >>> http://review.coreboot.org/coreboot.git ./ >>> poplinux@raw work $ > cd coreboot >>> poplinux@raw coreboot $ > git submodule update --init --checkout >>> >>> Next, *run make menuconfig* and set-up to mohon peak CRB and save & exit >>> >>> * Mainboa**rd* >>> Mainboard vendor (*Intel*) ---> >>> Mainboard model (*Mohon Peak CRB*) ---> >>> [ ] Configure defaults for the Intel FSP package >>> ROM chip size (2048 KB (2 MB)) ---> >>> (0x00200000) Size of CBFS filesystem in ROM >>> () fmap description file in fmd format >>> >>> Next, I'm try to build core boot. >>> >>> poplinux@raw coreboot $ > make >>> GEN generated/bootblock.ld >>> CP bootblock/arch/x86/bootblock.ld >>> LINK cbfs/fallback/bootblock.debug >>> OBJCOPY cbfs/fallback/bootblock.elf >>> OBJCOPY bootblock.raw.bin >>> Checking out SeaBIOS revision >>> 01a84bea2d28a19d2405c1ecac4bdef17683cc0c >>> Switched to branch 'master' >>> >>> Performing operation on 'COREBOOT' region... >>> Name Offset Type Size >>> cbfs master header 0x0 cbfs header 32 >>> fallback/romstage 0x80 stage 22684 >>> cpu_microcode_blob.bin 0x5980 microcode 0 >>> config 0x5a00 raw 127 >>> revision 0x5ac0 raw 570 >>> cmos_layout.bin 0x5d40 cmos_layout 1316 >>> fallback/dsdt.aml 0x62c0 raw 7952 >>> payload_config 0x8240 raw 1574 >>> payload_revision 0x88c0 raw 237 >>> (empty) 0x8a00 null 29848 >>> mrc.cache 0xfec0 mrc_cache 65536 >>> fallback/ramstage 0x1ff00 stage 46922 >>> fallback/payload 0x2b6c0 payload 61122 >>> (empty) 0x3a5c0 null 1856216 >>> bootblock 0x1ff8c0 bootblock 1528 >>> >>> Finally, I'm got a coreboot image. >>> >>> >>> poplinux@raw build $ > ls build/coreboot.rom >>> build/coreboot.rom >>> poplinux@raw build $ > ./build/cbfstool build/coreboot.rom print >>> Performing operation on 'COREBOOT' region... >>> Name Offset Type Size >>> cbfs master header 0x0 cbfs header 32 >>> fallback/romstage 0x80 stage 22684 >>> cpu_microcode_blob.bin 0x5980 microcode 0 >>> config 0x5a00 raw 127 >>> revision 0x5ac0 raw 570 >>> cmos_layout.bin 0x5d40 cmos_layout 1316 >>> fallback/dsdt.aml 0x62c0 raw 7952 >>> payload_config 0x8240 raw 1574 >>> payload_revision 0x88c0 raw 237 >>> (empty) 0x8a00 null 29848 >>> mrc.cache 0xfec0 mrc_cache 65536 >>> fallback/ramstage 0x1ff00 stage 46922 >>> fallback/payload 0x2b6c0 payload 61122 >>> (empty) 0x3a5c0 null 1856216 >>> bootblock 0x1ff8c0 bootblock 1528 >>> >>> >>> And I'm write image to my EVB using *ALL-100 Gang-writ**er*. >>> spi flash's write *start address is set 0x00000000*. write it success. >>> >>> And I'm attach the flash memory to my EVB. >>> >>> And power-up the my EVB. But can't see any message on my monitor and >>> serial port both. >>> >>> >>> *Why did not display any message? * >>> *A**nd could you support correct configuration file for my EVB?* >>> >>> Thank you. >>> >>> >>> >>> >>> >>> >>> -- >>> coreboot mailing list: [email protected] >>> http://www.coreboot.org/mailman/listinfo/coreboot >> >> >> >> -- >> coreboot mailing list: [email protected] >> http://www.coreboot.org/mailman/listinfo/coreboot >> > >
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