-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 02/15/2017 08:07 AM, Daniel Kulesz via coreboot wrote: > Hi folks, > > after a lengthy bisection run I was able to nail down the commit which is > causing the MC4 errors in the configurations I tested. I reverted the commit > on top of current master, and now my KGPE-D16 fully works without MC4 errors > in both 1-CPU-package und 2-CPU-package configurations - that is, with all 16 > memory slots populated with the 8GB DDR3L Samsung RDIMMs (PC12800 variant) > mentioned in my initial post.
Thank you for working on that bisect, and for isolating the exact commit causing the problem! However, we are going to need additional input from other owners of the KGPE-D16 to verify that a simple revert does not break support for the DIMMs installed in their machines. In particular, I am interested in test reports from those with Kingston RDIMMs since they seemed to be among the most finicky. > However, the issue with memory clock (being reported at) 667MHz in dmidecode > still remains. Can you please send over a debug log at SPEW level showing the romstage boot process for 4 DIMMs? The only log I have right now is for 8. Thanks! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJYpIBjAAoJEK+E3vEXDOFbCkcH/Rq4i+UD+Ow13LKPczZmwUAL YXSPkCx4dJBRxBxB0BV9ikzsRpLC91hkxqg6T4RN+Bgla8hQF+Gj17PV9D/S9Kif +O0b7F8NVcx1hY1RPSWztm7fcWCz40yrla0JCSSVNkkWEGQVrCx9KgxIcsS2YmIC iKGuTxDUSN63WSBNqMxpYcwH88iJZQiPM3/cOp2EZ6dLCWgeGEhWyDlkbvwK+VFr cyuibAU2zgCLU2wlQ/30uCnoFCbdNCQ4m+YfVCeeU0DlJDO18OOsC5azogG0MASr 7PnUIqqsmKa8TciJPPTsXi/LZmlsZry9Db2GXOvKRb72NXviIKhbxZ0UBZRtnxc= =YsB1 -----END PGP SIGNATURE----- -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
