Hi, > > after a lengthy bisection run I was able to nail down the commit which is > > causing the MC4 errors in the configurations I tested. I reverted the > > commit on top of current master, and now my KGPE-D16 fully works without > > MC4 errors in both 1-CPU-package und 2-CPU-package configurations - that > > is, with all 16 memory slots populated with the 8GB DDR3L Samsung RDIMMs > > (PC12800 variant) mentioned in my initial post. > > Thank you for working on that bisect, and for isolating the exact commit > causing the problem! > > However, we are going to need additional input from other owners of the > KGPE-D16 to verify that a simple revert does not break support for the > DIMMs installed in their machines. In particular, I am interested in > test reports from those with Kingston RDIMMs since they seemed to be > among the most finicky. >
I have some more DIMMs I could test with if this would help: - 2x Samsung 2GB 8500R - 6x Crucial Ballistix Sport (non-RDIMMs, 4 of them have issues in another vendor bios running at the clock specified in the SPD) > > However, the issue with memory clock (being reported at) 667MHz in > > dmidecode still remains. > > Can you please send over a debug log at SPEW level showing the romstage > boot process for 4 DIMMs? The only log I have right now is for 8. > Yep, will do so! Cheers, Daniel -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
