Paul Menzel via coreboot <[email protected]> writes:
> I think most of the time is spent in RAM initialization. > > 1. Do board owners with similar amount of memory (independent of the > board) have similar numbers? > 2. What are the ways to improve that? Is it possible? For example, can > the modules be probed in parallel (if that isn’t done already)? > I'm not the right person to answer this since I don't know this code/hardware that well, but on modern Intel hardware native code uses the MRC cache to store dram training results and restore those on next boots (and resume from suspend) if no change in dimm configuration was detected. Maybe something like this could also be applied here (or maybe it's already the case since it includes code to access spi flash)? > > Thanks, > > Paul Kind regards -- Arthur Heymans -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
