Dear Arthur, dear Timothy,
Am Donnerstag, den 02.03.2017, 13:38 -0600 schrieb Timothy Pearson: > On 03/02/2017 01:30 PM, Arthur Heymans wrote: > > Paul Menzel writes: > > > > > I think most of the time is spent in RAM initialization. > > > > > > 1. Do board owners with similar amount of memory (independent of the > > > board) have similar numbers? > > > 2. What are the ways to improve that? Is it possible? For example, can > > > the modules be probed in parallel (if that isn’t done already)? > > > > > > > I'm not the right person to answer this since I don't know this > > code/hardware that well, but on modern Intel hardware native code uses > > the MRC cache to store dram training results and restore those on > > next boots (and resume from suspend) if no change in dimm configuration > > was detected. > > > > Maybe something like this could also be applied here (or maybe it's already > > the case since it includes code to access spi flash)? > > Yes, this is already implemented as an option, and it does a fairly > decent job of reducing training overhead to almost nothing, Interesting. What option is that? Also, besides the file `s3nv` I don’t see anything else in CBFS. Where is the training data cached? […] Thanks, Paul
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