Hi What target are you on?
Coreboot tries to locate all PCI BAR's below 4G in the PCI_MMIO region and above the lower DRAM limit (the rest of the DRAM is mapped above 4G). Typically a GPU takes around 256M but I guess that could be more nowadays. If that doesn't fit in the PCI MMIO region, it will have troubles and probably not boot. The real fix would be to have coreboot locate BAR's above 4G too. At least that is what I think is going on here... (sry for top posting it felt like the answer was better in one block) Adam Talbot <[email protected]> writes: > -Coreboot > I am totally off the deep end and don't know where else to turn for > help/advice. I am trying to get 16 GPU's on one motherboard. Whenever I > attach more then 3~5 GPU's to a single motherboard, it fails to post. To make > matters worse, my post > code reader(s) don't seem to give me any good error codes. Or at least > nothing I can go on. > > I am using PLX PEX8614 chips (PCIe 12X switch) to take 4 lanes and pass them > to 8 GPU's, 1 lane per GPU. Bandwidth is not an issues as all my code runs > native on the GPUs. Depending on the motherboard, I can get up to 5 GPU's to > post. After > many hours of debugging, googling, and trouble shooting, I am out of ideas. > > At this point I have no clue. I think there is a hardware, and a BIOS > component? Can you help me understand the post process and where the hang up > is occurring? Do you think Coreboot will get around this hangup and, if so, > can you advise a > motherboard for me to test with? > > Its been a long time sense I last compiled linuxbios. ;-) > > Thanks > -Adam Kind regards -- Arthur Heymans -- coreboot mailing list: [email protected] https://mail.coreboot.org/mailman/listinfo/coreboot
