Frans Hendriks wrote:
> Hi Michal,
>
Hi Frans,
> We have implemented coreboot on Braswell SoC (Pentium N3170) using SPD.
>
> Did you verify the UDP fields: PcdMemoryTypeEnable, PcdMemorySpdPtr
> PcdMemChannel0Config
> and
> PcdMemChannel1Config?
>
These are settings I use in devicetree.cb:
register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "1"
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
Secondly, using common Intel SoC SMBus block implementation, I retrieve
SPD from DIMM and pass it to PcdMemorySpdPtr. Then setting
PcdMemChannel0Config to 1 (soldered down memory) and
PcdMemChannel0Config to 2 (DIMM disabled, because only the first channel is
populated). PcdMemoryTypeEnable is left the default to 0 (DDR3) which should
be correct.
> Do you have some coreboot/FSP logging?
>
Here are the logs from Celeron J3160 (I have applied few of Your patches
locally, C_ENV_BOOTBLOCK and FSP MR2 support):
1. Using FSP MR2:
coreboot-4.9-312-gc316fc82b8 Sat Jan 26 19:00:59 UTC 2019 bootblock
starting...
CBFS @ 320000 size 4e0000
CBFS: 'Master Header Locator' located CBFS at [320000:800000)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 9564
coreboot-4.9-312-gc316fc82b8 Sat Jan 26 19:00:59 UTC 2019 romstage
starting...
CBFS @ 320000 size 4e0000
CBFS: 'Master Header Locator' located CBFS at [320000:800000)
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 3fffc0 size 4cc00
POST: 0x30
CBFS @ 320000 size 4e0000
CBFS: 'Master Header Locator' located CBFS at [320000:800000)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 482780 size 44800
microcode: sig=0x406c4 pf=0x1 revision=0x410
CONFIG_MMCONF_BASE_ADDRESS: 0xe0000000
Using FSP 1.1
FSP_INFO_HEADER: fff20094
FSP Signature: BSWSBFSP
FSP Header Version: 2
FSP Revision: 1.1.4.1
FSP Entry Points:
0xfff20000: Image Base
0xfff6baa8: TempRamInit
0xfff6bc01: FspInit
0xfff6bc0f: MemoryInit
0xfff6bc16: TempRamExit
0xfff6bc1d: SiliconInit
0xfff6bc08: NotifyPhase
0xfff6cc00: Image End
pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00000000
gpe0_sts: 00000000 gpe0_en: 00000000 tco_sts: 00000000
prsts: 00040910 gen_pmcon1: 00245208 gen_pmcon2: 00000000
prev_sleep_state 5
SPD @ 0x50
SPD: module type is DDR3
SPD: module part is M471B5273DH0-YK0
SPD: banks 8, ranks 2, rows 15, columns 10, density 2048 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 4096 MB (per channel)
POST: 0x32
POST: 0x33
FMAP: Found "FLASH" version 1.1 at 300000.
FMAP: base = ff800000 size = 800000 #areas = 4
FMAP: area RW_MRC_CACHE found @ 310000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
No MRC cache found.
POST: 0x34
VPD Data: 0xfff6452c
UPD Data: 0xfff63494
Updating UPD values for MemoryInit
POST: 0x36
UPD values for MemoryInit:
0x0004 --> 0x0008: PcdMrcInitTsegSize
0x0800: PcdMrcInitMmioSize
0xa0: PcdMrcInitSpdAddr1
0xa2: PcdMrcInitSpdAddr2
0x00 --> 0x01: PcdMemChannel0Config
0x00 --> 0x02: PcdMemChannel1Config
0x00000000 --> 0xfef02ea0: PcdMemorySpdPtr
0x01: PcdIgdDvmt50PreAlloc
0x02: PcdApertureSize
0x01: PcdGttSize
0x00: PcdLegacySegDecode
0x01 --> 0x00: PcdDvfsEnable
Calling FspMemoryInit: 0xfff6bc0f
0x00000000: NvsBufferPtr
0xfef01de4: RtBufferPtr
0xfef01d8c: HobListPtr
POST: 0x92
2. Using FSP MR1:
coreboot-4.9-312-gc316fc82b8 Sat Jan 26 19:00:59 UTC 2019 bootblock
starting...
CBFS @ 320000 size 4e0000
CBFS: 'Master Header Locator' located CBFS at [320000:800000)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 9564
coreboot-4.9-312-gc316fc82b8 Sat Jan 26 19:00:59 UTC 2019 romstage
starting...
CBFS @ 320000 size 4e0000
CBFS: 'Master Header Locator' located CBFS at [320000:800000)
CBFS: Locating 'fsp.bin'
CBFS: Found @ offset 3fffc0 size 48800
POST: 0x30
CBFS @ 320000 size 4e0000
CBFS: 'Master Header Locator' located CBFS at [320000:800000)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 482780 size 44800
microcode: sig=0x406c4 pf=0x1 revision=0x410
CONFIG_MMCONF_BASE_ADDRESS: 0xe0000000
Using FSP 1.1
FSP_INFO_HEADER: fff20094
FSP Signature: $BSWFSP$
FSP Header Version: 2
FSP Revision: 1.1.2.0
FSP Entry Points:
0xfff20000: Image Base
0xfff676a8: TempRamInit
0xfff67801: FspInit
0xfff6780f: MemoryInit
0xfff67816: TempRamExit
0xfff6781d: SiliconInit
0xfff67808: NotifyPhase
0xfff68800: Image End
pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00000000
gpe0_sts: 00000000 gpe0_en: 00000000 tco_sts: 00000000
prsts: 00040910 gen_pmcon1: 00245208 gen_pmcon2: 00000000
prev_sleep_state 5
SPD @ 0x50
SPD: module type is DDR3
SPD: module part is M471B5273DH0-YK0
SPD: banks 8, ranks 2, rows 15, columns 10, density 2048 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 4096 MB (per channel)
POST: 0x32
POST: 0x33
FMAP: Found "FLASH" version 1.1 at 300000.
FMAP: base = ff800000 size = 800000 #areas = 4
FMAP: area RW_MRC_CACHE found @ 310000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
No MRC cache found.
POST: 0x34
VPD Data: 0xfff4a39c
UPD Data: 0xfff4a3b0
Updating UPD values for MemoryInit
POST: 0x36
UPD values for MemoryInit:
0x0004 --> 0x0008: PcdMrcInitTsegSize
0x0800: PcdMrcInitMmioSize
0xa0: PcdMrcInitSpdAddr1
0xa2: PcdMrcInitSpdAddr2
0x00 --> 0x01: PcdMemChannel0Config
0x00 --> 0x02: PcdMemChannel1Config
0x00000000 --> 0xfef02ea0: PcdMemorySpdPtr
0x01: PcdIgdDvmt50PreAlloc
0x02: PcdApertureSize
0x01: PcdGttSize
0x00: PcdLegacySegDecode
0x01 --> 0x00: PcdDvfsEnable
Calling FspMemoryInit: 0xfff6780f
0x00000000: NvsBufferPtr
0xfef01de4: RtBufferPtr
0xfef01d8c: HobListPtr
POST: 0x92
After the post code 0x92 platform seems to not going any further. The
dump is from the serial port on SuperIO.
> Best regards,
> Frans Hendriks
> Eltan B.V.
>
Thank You in advance.
Best regards,
Michał
> -----Original Message-----
> From: Michal Zygowski [mailto:[email protected]]
> Sent: maandag 28 januari 2019 15:48
> To: coreboot(a)coreboot.org
> Cc: Piotr Król <piotr.krol(a)3mdeb.com>
> Subject: [coreboot] Braswell FPS memory init problems
>
> Dear coreboot community,
>
> I am experiencing problems with FSP Memory Init on Braswell SoCs. FSP Memory
> Init is not
> returning. I have following processors that fail:
> Celeron J3060 and Celeron J3160; both have the same issue.
>
> The platform has 1 SODIMM module on channel 0. I am feeding the UPD header
> with correct
> SPD, but still no luck. I have also tried FSP MR1 and MR2, but nothing works.
>
> Is anyone here more experienced with Braswell platforms? Could You give me
> some advices?
>
> Best regards,
>
> --
> Michał Żygowski
> Embedded Systems Engineer
> http://3mdeb.com | @3mdeb_com
>
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