Hi, I am wondering what is the format of CPU-DRAM DQ byte map for FSP-M configuration. Typically there are 64 DQ lanes per non-ECC SODIMM/DIMM (correct me if I'm wrong) for DDR4 for example. But the DQ map is an 2x12 array, so I assume 12 bytes for each channel (why not 8 bytes?). My questions are:
1. Why there are more bytes in array than DQ lanes? 2. How should I define the DQ map? Does 0xFF or 0x00 mean 1 to 1 mapping? 3. Some FSP2.0 mainboards have values like 0x0F and 0xF0 in their mappings which looks like 1 byte swap, but there are also 0xCC and 0x33. What is the difference? The DQS mapping is clear to me (rather obvious as there are only 8 DQS which matches the 2x8 array). I know about 3 Rcomp resistors of the chipset and what they are for, but what RcompTarget is? In the code I can see function `mainboard_fill_rcomp_strength_data` and begin to wonder what rcomp strength is (not Rcomp Target?). How to correctly fill RcompTarget FSP-M configuration? Any tips and pointers appreciated. Regards, -- Michał Żygowski Firmware Engineer http://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
