DDR RComp calculation is explained in the CPU platform design guide. If you are an Intel licensee, you can request this document by number - 561280 for KBL. There seems to be also a whitepaper you can ask your OEM rep for. The actual values are calculated based on memory topology and board layout and then fine-tuned through measurement. Basically, if you are a system designer, you have the documents and know how to do it, and if you are not, then these values are calculated by the manufacturer/BIOS writer so your only recourse is to find out from them.
Similarly, DQ array is filled according to the information supplied by the system designer. Intel CPUs allow certain freedom in routing the memory pins to simplify the board layout task. The pin map should be filled for DQ/DQS according to the physical connectivity chosen by the system designer. Bottom line - it's not something you can figure out by looking at a motherboard ________________________________________ From: Nico Huber <[email protected]> Sent: Friday, March 29, 2019 10:03 AM To: Michal Zygowski; [email protected] Subject: [coreboot] Re: FSP2.0 DQ byte map Hi Michal, On 29.03.19 16:49, Michal Zygowski wrote: > I am wondering what is the format of CPU-DRAM DQ byte map for FSP-M > configuration. Typically there are 64 DQ lanes per non-ECC SODIMM/DIMM > (correct me if I'm wrong) for DDR4 for example. But the DQ map is an > 2x12 array, so I assume 12 bytes for each channel (why not 8 bytes?). My > questions are: > > 1. Why there are more bytes in array than DQ lanes? it's actually not an array but a rather complex structure. You can find some clues in the Skylake FSP Integration Guide [1] and also in coreboot header files [2]. I have no idea why the documentation was removed from future guides. > 2. How should I define the DQ map? Does 0xFF or 0x00 mean 1 to 1 mapping? If you have DDR4 (SO)DIMMs, you probably shouldn't. [2] mentions that it's for memory-down configurations with LPDDR3 only. And, AFAIR, an investigation into the deep of the KBL FSP source didn't find any relation to DDR4. > I know about 3 Rcomp resistors of the chipset and what they are for, but > what RcompTarget is? > In the code I can see function `mainboard_fill_rcomp_strength_data` and > begin to wonder what rcomp strength is (not Rcomp Target?). How to > correctly fill RcompTarget FSP-M configuration? Please tell me if you find out ;) even Intel developers working on coreboot don't know. Some insider came back quoting identifiers from comments in the FSP header... identifiers nowhere to be found in source/documentation. My guess is that the targets are either computed or even measured by some very confidential tool. Nico [1] https://github.com/IntelFsp/FSP/raw/master/SkylakeFspBinPkg/Docs/SkylakeFspIntegrationGuide.pdf [2] https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/broadwell/include/soc/pei_data.h#n236 _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected] _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
