Hi Naveen, What does "Configuration not in POR table mean? Does this mean that FSP can > no longer initialize my DRAM automatically? If yes, what's the solution > here? Or shall I try tweaking other settings such as MemEccSupport, > MemDdrMemoryType, etc. >
Intel validates several configurations of DRAM to go with their SoCs, and AFAIK validated parts are considered "POR" (plan of record?). 'ddrfreq = 255' is a weird value for DRAM frequency, so I suspect that is really an error code that indicates a problem with the frequency passed in via your configuration or SPDs. So you may need to adjust the value to match common DDR4 timings, such as DDR4 2133 or DDR4 2400. The following documents might help to figure out a valid configuration for your SoC (you'll need to download them from Intel yourself, of course): Document number 543448 - Grangeville Platform Design Guide Document number 557970 - Xeon D-1500 Specification update
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