Thanks David for the response. Does this mean that there is a way in FSP to define custom settings(configs) for DIMMs? In the FSP integration guide for BroadwellDE (https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/Docs) I don't see any relevant data member where we could define pointer to custom SPD settings or pass individual DIMMs configurations.
Hence, I was assuming that the only way DIMM memory could be initialized is that FSP itself will locate SPD and will apply the whatever read settings. Meanwhile, I am going through the documents. Since I also have the datasheet available for the DIMMs, I can try playing with different settings, but I need to know a way to do that, which till now I was assuming that there is no such way. Waiting to hear back. Many thanks. Regards, Naveen [https://avatars1.githubusercontent.com/u/19785541?s=400&v=4]<https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/Docs> FSP/BroadwellDEFspBinPkg/Docs at master ยท IntelFsp/FSP - github.com<https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/Docs> Intel(R) Firmware Support Package (FSP). Contribute to IntelFsp/FSP development by creating an account on GitHub. github.com ________________________________ From: David Hendricks <[email protected]> Sent: Saturday, October 26, 2019 7:29 AM To: Naveen Chaudhary <[email protected]> Cc: [email protected] <[email protected]> Subject: Re: [coreboot] Coreboot FSP fails to initialize RAM - "Configuration not in POR table" Hi Naveen, What does "Configuration not in POR table mean? Does this mean that FSP can no longer initialize my DRAM automatically? If yes, what's the solution here? Or shall I try tweaking other settings such as MemEccSupport, MemDdrMemoryType, etc. Intel validates several configurations of DRAM to go with their SoCs, and AFAIK validated parts are considered "POR" (plan of record?). 'ddrfreq = 255' is a weird value for DRAM frequency, so I suspect that is really an error code that indicates a problem with the frequency passed in via your configuration or SPDs. So you may need to adjust the value to match common DDR4 timings, such as DDR4 2133 or DDR4 2400. The following documents might help to figure out a valid configuration for your SoC (you'll need to download them from Intel yourself, of course): Document number 543448 - Grangeville Platform Design Guide Document number 557970 - Xeon D-1500 Specification update
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