Hi, Perhaps you are right. I was going through "Embedded Firmware Solutions" and on Page 43 :
"This S3 resume path (i.e., resume from a sleep state using existing memory contents) is used to optimize the boot speed by using the memory parameters passed in (instead of going through the memory training code). It can also be used for soldered-down memory configuration, or after the first boot when there is no change in memory configuration and when memory training parameters remain valid. There is not a “Fast Boot” flag to reflect the need to skip memory training, but FSP will look at the input parameter, NvsBufferPtr, to determine if it should skip memory training or not. If it is NULL, it will not skip, and if there is a valid pointer stored in NvsBufferPtr, it will skip the memory training code. This can save potential boot time up to 100 milliseconds." And for recent SoCs, we even have FastBoot flag now. This could be the way out. This way we can prevent the FSP from reading SPD and rather read from the NVRAM. But I am not sure what should be the structure for NvsBuffer pointer. Perhaps, I may create a structure of 512 bytes on stack as per JEDEC spec for DIMMs, and then pass that to the API. If my assumption is correct, to begin with I can pass the exact same SPD data as on the RAM SPD (by referring the datasheet), so that I get the same behaviour. Next, I can experiment changing the values. Has anyone on this mailing thread experience working with custom DIMMs that aren't POR for FSP? How did you come through this problem? Need your experience here guys. Please help. Regards, Naveen ________________________________ From: Nico Huber <[email protected]> Sent: Sunday, October 27, 2019 4:03 PM To: Naveen Chaudhary <[email protected]>; David Hendricks <[email protected]> Cc: [email protected] <[email protected]> Subject: Re: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table" Hello Naveen, On 27.10.19 05:02, Naveen Chaudhary wrote: > Does this mean that there is a way in FSP to define custom settings(configs) > for DIMMs? In the FSP integration guide for BroadwellDE > (https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/Docs) I > don't see any relevant data member where we could define pointer to custom > SPD settings or pass individual DIMMs configurations. there is the memory-down option. It seems undocumented if that does more than switching from on-DIMM SPDs to SPD files. Maybe it's worth a try. If that doesn't work out, you can always overwrite the SPDs on your DIMM's EEPROMs. Always keep a backup, though. Hope that helps, Nico
_______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
