Hi Ashok,
Am 26.06.26 um 07:16 schrieb Ashok Arora:
Hi all,
I am planning to port coreboot to the *Enter ATX E-G41D2*(Intel G41 +
ICH7), a low-cost, popular alternative to the supported *Gigabyte GA-
G41M-ES2L*in the Indian market.
Using the |gigabyte/ga-g41m-es2l| port as a baseline, I have a few quick
questions before I begin:
1.
*GPIO Mapping:* Is dumping registers via |inteltool| the most
reliable method to identify ICH7 GPIO differences from the vendor BIOS?
yes, absolutely. You may want to use the intelp2m tool afterwards to
turn the output of inteltool into C code for the gpio.h file.
I'm not sure from which comparison you want to draw those differences;
I'd start with just dumping the vendor bios' GPIO configuration and then
using that as a starting point in coreboot.
2.
*Super I/O Delta:* If the physical Super I/O chip differs from
Gigabyte's ITE IT8718F, which primary configuration files (aside
from |Kconfig| and |devicetree.cb|) require updates?
If you're in luck, you'd just adjust devicetree.cb with the correct
superio chip (if already supported) and tune some settings. If coreboot
does not support your chip already, you may need to write some code
inside src/superio/.
3.
*Native Raminit:* Are there any known routing or DIMM slot layout
edge cases that cause native |x4x| raminit to fail on non-reference
boards?
Not that I know of. It will likely "just work" if the RAM SPDs are on
the default addresses, and if not, you'll figure it out ;). (Worst-case
is that raminit fails, but there should be no hardware damage, so you
can just try it out.)
Happy hacking!
Florian
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Florian Jung
Development
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