Hi Ashok, > On 2026-06-26 05:36, Florian Jung via coreboot wrote: > Hi Ashok, > > Am 26.06.26 um 07:16 schrieb Ashok Arora: >> Hi all, >> I am planning to port coreboot to the *Enter ATX E-G41D2*(Intel G41 + >> ICH7), a low-cost, popular alternative to the supported *Gigabyte GA- >> G41M-ES2L*in the Indian market. >> >> Using the |gigabyte/ga-g41m-es2l| port as a baseline, I have a few >> quick questions before I begin: >> >> 1. >> >> *GPIO Mapping:* Is dumping registers via |inteltool| the most >> reliable method to identify ICH7 GPIO differences from the vendor >> BIOS? > > yes, absolutely. You may want to use the intelp2m tool afterwards to > turn the output of inteltool into C code for the gpio.h file.
Intelp2m only supports Skylake and newer, for older platforms there is https://codeberg.org/Riku_V/gpio-scripts. Note that this will include GPIOs that don't actually exist on ICH7, namely all of gpio set 3 and some GPIOs in set 2. Refer to the ICH7 datasheet for which GPIOs are actually present. >> 2. >> >> *Super I/O Delta:* If the physical Super I/O chip differs from >> Gigabyte's ITE IT8718F, which primary configuration files (aside >> from |Kconfig| and |devicetree.cb|) require updates? > > If you're in luck, you'd just adjust devicetree.cb with the correct > superio chip (if already supported) and tune some settings. If coreboot > does not support your chip already, you may need to write some code > inside src/superio/. > Some Super I/Os may also need code in files like early_init.c or bootblock.c for things like setting up serial ports (for the debug console output) and disabling timers that will reboot the system. Cheers, Nicholas _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
