At 09:54 PM 5/24/00 -0500, Jim Choate wrote:
>As to inserting a trapdoor in an FPGA, I don't see any reason at all that
>a trapdoor can't be inserted with the appropriate understanding of the
>state space and chosing a rare state to trigger your bypass.

Yes but *once* you've verified the RTL (and from them the masks) 
you don't have to worry about some stray applet hosing your security.
You do with software.

A hardware bump in the wire (link encryptor), for instance is
very hard to get around (short of out of band 'tempest' et al. attacks)








  





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