On Tue, Jun 19, 2012 at 9:02 AM, <[email protected]> wrote: >... > It is not using AES-NI. It is a self contained unit on chip with a built > in HW AES encrypt block cipher.
thanks for the clarification; is this documented somewhere? i am curious if the die space consumed for two implementations of AES in negligable on these very large cores, or if there is another reason to intentionally keep them separate. _______________________________________________ cryptography mailing list [email protected] http://lists.randombit.net/mailman/listinfo/cryptography
