On 06/19/2012 01:59 PM, coderman wrote:
thanks for the clarification; is this documented somewhere? i am curious if the die space consumed for two implementations of AES in negligable on these very large cores, or if there is another reason to intentionally keep them separate.
It sounds to me like the AES CTR DRBG is shared between multiple cores. So keeping it independent of any one core sounds like a good reason to separate it.
But then design decisions for these chips have mystified me in the past. (HT, SMM, etc. :-)
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