Could this problem be becouse of "Advisory 1.1.6" on sprz241d.pdf (silicon errata) that stands: DDR2: Multiple Master Access to the DDR2 at the Same Time may Cause Master to Stop. Revision(s) Affected: 1.1
How could I know my silicon revision? How could I know DSP, ARM, VCLK and MCLK clock rates? Here are the details for this silicon errata: Details: If multiple Masters (CPUs or Master peripherals) are accessing the DDR2 Memory Controller simultaneously and at least one of the Masters is performing 64-byte burst transfers to the DDR2 Memory Controller, one of the Masters may stop, requiring a power-up reset to recover. Workaround: Reliable operation is achieved when the DDR2 Memory Controller VCLK and MCLK are set to a 1:1 ratio. The lockup is sensitive to non 1:1 frequency ratios between the clock used by the DDR2 Memory Controller (VCLK) and the clock used by the DDR2 PHY interface to the external bus (MCLK). For more detailed information on the clocks to the DDR2 Memory Controller, see the TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (literature number SPRUE22). The recommended clock configurations are: • DSP CPU clock at 486 MHz ARM CPU clock at 243 MHz VCLK at 162 MHz MCLK at 162 MHz • DSP CPU clock at 567 MHz ARM CPU clock at 283.5 MHz VCLK at 189 MHz MCLK at 189 MHz Note: A DDR2 clock rate of 189 MHz is only supported on silicon revision 1.1 as a workaround for this advisory. For silicon revisions 1.2 and later, see the device specific data manual for the DDR maximum clock rate supported. _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
