I am using the DaVinci to drive a 1024x768 LCD in RGB888 mode using DC5 as well. I have NO code running in the DSP (it is not being booted at all) and am not using Linux (I am using INTEGRITY). Also, I am only using VIDWIN0. However, the problem described by this thread sounds like an issue with which I have been wrestling. The OSD appears shifted for just a frame time and then goes back. It seems to occur most often when I am moving data with memcpy. If the data block being copied is less than 4K, thing seem ok. But if the block is larger than that, the larger the block the more often frames are shifted. As a result I have changed my video drivers to move my video data using DMA and this seemed much better. But, still if I use memcpy or memset to modify a block of data larger than 4K, the OSD shifts. I too, thought it could be related to Advisory 1.1.6. After changing my clock rates to be within the Advisories recommendations, I am still having the problem. I am at a loss as to what to do next!
-----Original Message----- Message: 1 Date: Wed, 13 Dec 2006 11:37:51 +0100 From: "Carlos Ojea" <[EMAIL PROTECTED]> Subject: Re: OSD shifted when executing code on DSP To: [email protected] Message-ID: <[EMAIL PROTECTED]> Content-Type: text/plain; charset=ISO-8859-1; format=flowed (I am using rgb888 mode) ------------------------------ Message: 2 Date: Wed, 13 Dec 2006 12:46:27 +0100 From: "Carlos Ojea" <[EMAIL PROTECTED]> Subject: Re: OSD shifted when executing code on DSP To: [email protected] Message-ID: <[EMAIL PROTECTED]> Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Could this problem be becouse of "Advisory 1.1.6" on sprz241d.pdf (silicon errata) that stands: DDR2: Multiple Master Access to the DDR2 at the Same Time may Cause Master to Stop. Revision(s) Affected: 1.1 How could I know my silicon revision? How could I know DSP, ARM, VCLK and MCLK clock rates? Here are the details for this silicon errata: Details: If multiple Masters (CPUs or Master peripherals) are accessing the DDR2 Memory Controller simultaneously and at least one of the Masters is performing 64-byte burst transfers to the DDR2 Memory Controller, one of the Masters may stop, requiring a power-up reset to recover. Workaround: Reliable operation is achieved when the DDR2 Memory Controller VCLK and MCLK are set to a 1:1 ratio. The lockup is sensitive to non 1:1 frequency ratios between the clock used by the DDR2 Memory Controller (VCLK) and the clock used by the DDR2 PHY interface to the external bus (MCLK). For more detailed information on the clocks to the DDR2 Memory Controller, see the TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (literature number SPRUE22). The recommended clock configurations are: DSP CPU clock at 486 MHz ARM CPU clock at 243 MHz VCLK at 162 MHz MCLK at 162 MHz DSP CPU clock at 567 MHz ARM CPU clock at 283.5 MHz VCLK at 189 MHz MCLK at 189 MHz Note: A DDR2 clock rate of 189 MHz is only supported on silicon revision 1.1 as a workaround for this advisory. For silicon revisions 1.2 and later, see the device specific data manual for the DDR maximum clock rate supported. _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
