Viet,
There are GPIO Kernel APIs in the DM355 DVEVM software to use a GPIO pin
as an interrupt.
Here is an example how it was done for the DM9000A Ethernet controller.
// GPIO1 is Ethernet interrupt GPIO
u32 gpio = 1;
/* Enable interrupt generation from GPIO Bank 0 (GPIO0-GPIO15)
*/
gpio_interrupt_bank_enable(gpio);
/* Configure GPIO1 as an input */
gpio_set_direction(gpio, GIO_DIR_INPUT);
/* Configure GPIO1 to generate an interrupt on rising edge only
*/
gpio_interrupt_enable(gpio, TRIGGER_RISING_EDGE);
gpio_interrupt_disable(gpio, TRIGGER_FALLING_EDGE);
In your case, you would need to configure GPIO6 as an in input and then
configure it to generate an interrupt on falling edge. You would also
need to setup the interrupt handler for IRQ_DM355_GPIO6.
Sneha
________________________________
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On
Behalf Of Viet Hoang
Sent: Saturday, March 01, 2008 1:34 AM
To: [email protected]
Subject: IRQ_DM355_GPIO6: Write to CLR_RIS_TRIG01 clears this register.
Hi,
I want to use IRQ_DM355_GPIO6 interrupt, I configure the GPIO6 pin
so that it generates an interrupt only at falling edge.
Below is my code:
long status;
poweron_gpio();
//set bit in BINTEN:: BANK0 , GPIO pin no. 6.
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x08));
printk("[Viet]::BINTEN = %x", status);
status |= 0x01;
__raw_writel( status, (( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x08)));
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x08));
printk("\tBINTEN = %x\n", status);
// clear raising edge of GPIO6
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28));
printk("[Viet]::CLR_RIS_TRIG01 = %x", status);
status |= 0x00000040;
printk("\tCLR_RIS_TRIG01 = %x", status);
__raw_writel( status, (( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28)));
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28));
printk("\tCLR_RIS_TRIG01 = %x\n", status);
// set falling edge of GPIO6
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x2C));
printk("[Viet]::SET_FAL_TRIG01 = %x", status);
status |= 0x40;
printk("\tSET_FAL_TRIG01 = %x", status);
__raw_writel( status, (( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x2C)));
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x2C));
printk("\tSET_FAL_TRIG01 = %x\n", status);
And here are the messages during kernel's boot:
..........
[Viet]::BINTEN = 1 BINTEN = 1
[Viet]::CLR_RIS_TRIG01 = 2 CLR_RIS_TRIG01 = 42 CLR_RIS_TRIG01 =
0
[Viet]::SET_FAL_TRIG01 = 0 SET_FAL_TRIG01 = 40 SET_FAL_TRIG01 =
40
..........
At the 2nd line, you can see the code cannot write 0x42 to
CLR_RIS_TRIG01 register, it even clears that register to 0x0, that
clears the raising edge ethernet interrupt and causes the DHCP's failure
then
(
eth0: link down
Sending DHCP requests .<6>eth0: link up, 100Mbps, full-duplex, lpa
0x45E1
..<6>NETDEV WATCHDOG: eth0: transmit timed out
.<6>NETDEV WATCHDOG: eth0: transmit timed out
)
Do you know why? Please give me an advice.
Thanks,
Viet Hoang.
Send instant messages to your online friends
http://uk.messenger.yahoo.com
_______________________________________________
Davinci-linux-open-source mailing list
[email protected]
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
