Viet,
Sorry for the delay, I had to confirm this with the hardware team.
There are few basic facts with the GPIO that we need to understand -
1. Reading CLR (RIS or FAL) register returns the complement state
of the GPIO pins. If you read a 1 for a particular GPIO pin, this means
the interrupt is not disabled, while if you read a 0, the interrupt is
disabled for that particular pin.
2. For the rising interrupt or the falling interrupt registers
(set or clear), reading either register will always return the state of
whether the function is enabled in either case. If you enable rising
edge interrupts by writing a one to a GPIO bit in the SET_RIS_TRIG
register, you will read a one back in that bit in both registers
(SET_RIS_TRIG and CLR_RIS_TRIG). Reading back a zero in either register
[however will be in both] indicates that rising edge triggered
interrupts are disabled for that bit.
3. Writing a zero to the CLR register has no effect.
With the code you were trying to develop, you tried to read the current
value from CLR_RIS_TRIG register (which should give you complemented
states) and then do an OR operation to the get GPIO6 rising interrupt
disabled, you also end up disabling the GPIO1 rising interrupt for the
Ethernet. You just have to set the bit corresponding to GPIO6, leaving
all other bits zero, since writing a zero has no effect.
// clear raising edge of GPIO6
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28));
printk("[Viet]::CLR_RIS_TRIG01 = %x", status);
status |= 0x00000040; --> Should be status = 0x00000040;
printk("\tCLR_RIS_TRIG01 = %x", status);
__raw_writel( status, (( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28)));
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28));
printk("\tCLR_RIS_TRIG01 = %x\n", status);
There is also issue with the gpio_interrupt_enable function, that does
not read the current value (and then do an OR operation) to set the
interrupts.
Thanks
Sneha
________________________________
From: Viet Hoang [mailto:[EMAIL PROTECTED]
Sent: Tuesday, March 04, 2008 10:19 PM
To: Narnakaje, Snehaprabha;
[email protected]
Subject: RE: IRQ_DM355_GPIO6: Write to CLR_RIS_TRIG01 clears this
register.
Hi Sneha,
Yes, of course it worked. I just don't want to receive an interrupt
at rising edge.
Thanks,
Viet Hoang.
"Narnakaje, Snehaprabha" <[EMAIL PROTECTED]> wrote:
Viet,
Could you please try enabling just the "falling edge" for GPIO6
interrupt and not disable the "rising edge"? Do you see both GPIO0
(Ethernet) and GPIO6 working in this case?
Thanks
Sneha
________________________________
From: Viet Hoang [mailto:[EMAIL PROTECTED]
Sent: Tuesday, March 04, 2008 1:18 AM
To: Viet Hoang; Narnakaje, Snehaprabha;
[email protected]
Subject: RE: IRQ_DM355_GPIO6: Write to CLR_RIS_TRIG01 clears this
register.
Hi,
Perhaps I was wrong when expecting 0x42...
After the 2-line C-code in board-dm355-evm.c: (int gpio = 1;)
gpio_interrupt_enable(gpio, TRIGGER_RISING_EDGE);
gpio_interrupt_disable(gpio, TRIGGER_FALLING_EDGE);
the SET_RIS_TRIG01 and CLR_FAL_TRIG01 registers should be 0x02, right?
And after my 2-line C code: ( int gpio = 6;)
gpio_interrupt_enable(gpio, TRIGGER_FALLING_EDGE);
gpio_interrupt_disable(gpio, TRIGGER_RISING_EDGE);
the SET_FAL_TRIG01 and CLR_RIS_TRIG01 registers should be 0x40.
I used below code to check:
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x24));
printk("[Viet]::1--SET_RIS_TRIG01 = 0x%x\n", status);
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28));
printk("[Viet]::1--CLR_FAL_TRIG01 = 0x%x\n", status);
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x2C));
printk("[Viet]::1--SET_FAL_TRIG01 = 0x%x\n", status);
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x30));
printk("[Viet]::1--CLR_RIS_TRIG01 = 0x%x\n\n", status);
// Enable interrupt generation from GPIO Bank 0 (GPIO0-GPIO15)
//gpio_interrupt_bank_enable( gpio);
// Configure GPIO6 as an input
gpio_set_direction(gpio, GIO_DIR_INPUT);
gpio_interrupt_enable(gpio, TRIGGER_FALLING_EDGE);
gpio_interrupt_disable(gpio, TRIGGER_RISING_EDGE);
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x24));
printk("[Viet]::2--SET_RIS_TRIG01 = 0x%x\n", status);
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28));
printk("[Viet]::2--CLR_FAL_TRIG01 = 0x%x\n", status);
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x2C));
printk("[Viet]::2--SET_FAL_TRIG01 = 0x%x\n", status);
status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x30));
printk("[Viet]::2--CLR_RIS_TRIG01 = 0x%x\n", status);
and the output:
[Viet]::1--SET_RIS_TRIG01 = 0x2
[Viet]::1--CLR_FAL_TRIG01 = 0x2
[Viet]::1--SET_FAL_TRIG01 = 0x0
[Viet]::1--CLR_RIS_TRIG01 = 0x0
[Viet]::2--SET_RIS_TRIG01 = 0x2
[Viet]::2--CLR_FAL_TRIG01 = 0x2
[Viet]::2--SET_FAL_TRIG01 = 0x40
[Viet]::2--CLR_RIS_TRIG01 = 0x40
It seems reasonable.
BUT, please notice the register's addresses, there seem to be a
permutation between CLR_RIS_TRIG01 & CLR_FAL_TRIG01 (In SPRUEE6A -
TMS320DM35x Digital Media System-on-Chip (DMSoC) General-Purpose
Input/Output (GPIO), at page 19, you can see CLR_RIS_TRIG01 is at 28h
and CLR_FAL_TRIG01 is at 30h offset).
Any expert, please confirm this?
Thanks,
Viet Hoang.
Viet Hoang <[EMAIL PROTECTED]> wrote:
Hi all,
Sneha, thanks for your reply.
Viet Hoang.
"Narnakaje, Snehaprabha" <[EMAIL PROTECTED]> wrote:
Viet,
Sneha
________________________________
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On
Behalf Of Viet Hoang
Sent: Saturday, March 01, 2008 1:34 AM
To: [email protected]
Subject: IRQ_DM355_GPIO6: Write to CLR_RIS_TRIG01 clears this register.
Thanks,
Viet Hoang.
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