Viet,
Could you please try enabling just the "falling edge" for GPIO6 interrupt and not disable the "rising edge"? Do you see both GPIO0 (Ethernet) and GPIO6 working in this case? Thanks Sneha ________________________________ From: Viet Hoang [mailto:[EMAIL PROTECTED] Sent: Tuesday, March 04, 2008 1:18 AM To: Viet Hoang; Narnakaje, Snehaprabha; [email protected] Subject: RE: IRQ_DM355_GPIO6: Write to CLR_RIS_TRIG01 clears this register. Hi, Perhaps I was wrong when expecting 0x42... After the 2-line C-code in board-dm355-evm.c: (int gpio = 1;) gpio_interrupt_enable(gpio, TRIGGER_RISING_EDGE); gpio_interrupt_disable(gpio, TRIGGER_FALLING_EDGE); the SET_RIS_TRIG01 and CLR_FAL_TRIG01 registers should be 0x02, right? And after my 2-line C code: ( int gpio = 6;) gpio_interrupt_enable(gpio, TRIGGER_FALLING_EDGE); gpio_interrupt_disable(gpio, TRIGGER_RISING_EDGE); the SET_FAL_TRIG01 and CLR_RIS_TRIG01 registers should be 0x40. I used below code to check: status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x24)); printk("[Viet]::1--SET_RIS_TRIG01 = 0x%x\n", status); status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28)); printk("[Viet]::1--CLR_FAL_TRIG01 = 0x%x\n", status); status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x2C)); printk("[Viet]::1--SET_FAL_TRIG01 = 0x%x\n", status); status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x30)); printk("[Viet]::1--CLR_RIS_TRIG01 = 0x%x\n\n", status); // Enable interrupt generation from GPIO Bank 0 (GPIO0-GPIO15) //gpio_interrupt_bank_enable( gpio); // Configure GPIO6 as an input gpio_set_direction(gpio, GIO_DIR_INPUT); gpio_interrupt_enable(gpio, TRIGGER_FALLING_EDGE); gpio_interrupt_disable(gpio, TRIGGER_RISING_EDGE); status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x24)); printk("[Viet]::2--SET_RIS_TRIG01 = 0x%x\n", status); status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x28)); printk("[Viet]::2--CLR_FAL_TRIG01 = 0x%x\n", status); status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x2C)); printk("[Viet]::2--SET_FAL_TRIG01 = 0x%x\n", status); status = __raw_readl(( void* __iomem)IO_ADDRESS( GPIO_BASE + 0x30)); printk("[Viet]::2--CLR_RIS_TRIG01 = 0x%x\n", status); and the output: [Viet]::1--SET_RIS_TRIG01 = 0x2 [Viet]::1--CLR_FAL_TRIG01 = 0x2 [Viet]::1--SET_FAL_TRIG01 = 0x0 [Viet]::1--CLR_RIS_TRIG01 = 0x0 [Viet]::2--SET_RIS_TRIG01 = 0x2 [Viet]::2--CLR_FAL_TRIG01 = 0x2 [Viet]::2--SET_FAL_TRIG01 = 0x40 [Viet]::2--CLR_RIS_TRIG01 = 0x40 It seems reasonable. BUT, please notice the register's addresses, there seem to be a permutation between CLR_RIS_TRIG01 & CLR_FAL_TRIG01 (In SPRUEE6A - TMS320DM35x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output (GPIO), at page 19, you can see CLR_RIS_TRIG01 is at 28h and CLR_FAL_TRIG01 is at 30h offset). Any expert, please confirm this? Thanks, Viet Hoang. Viet Hoang <[EMAIL PROTECTED]> wrote: Hi all, Sneha, thanks for your reply. Viet Hoang. "Narnakaje, Snehaprabha" <[EMAIL PROTECTED]> wrote: Viet, Sneha ________________________________ From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Viet Hoang Sent: Saturday, March 01, 2008 1:34 AM To: [email protected] Subject: IRQ_DM355_GPIO6: Write to CLR_RIS_TRIG01 clears this register. Thanks, Viet Hoang. Send instant messages to your online friends http://uk.messenger.yahoo.com Send instant messages to your online friends http://uk.messenger.yahoo.com _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source Send instant messages to your online friends http://uk.messenger.yahoo.com
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