static void enableDigitalOutput(int bEnable)
{
if (bEnable)
{
// Set PINMUX0 reg to enable LCD (all other settings are kept per
u-boot)
dispc_reg_merge(PINMUX0, PINMUX0_LOEEN, PINMUX0_LOEEN);
// Set PCR register for FULL clock
dispc_reg_out(VPBE_PCR, 0);
// Enable video clock output and inverse clock polarity
dispc_reg_out(VENC_VIDCTL, (VENC_VIDCTL_VLCKE |
VENC_VIDCTL_VLCKP));
// Enabling SYNC pulse width processing, and turning on horizontal
and vertical syncs
// dispc_reg_out(VENC_SYNCCTL, (VENC_SYNCCTL_SYSW|VENC_SYNCCTL_SYEV|
VENC_SYNCCTL_SYEH) );
// Setting DRGB Matrix registers back to default values
dispc_reg_out(VENC_DRGBX0, 0x00000400);
dispc_reg_out(VENC_DRGBX1, 0x00000576);
dispc_reg_out(VENC_DRGBX2, 0x00000159);
dispc_reg_out(VENC_DRGBX3, 0x000002cb);
dispc_reg_out(VENC_DRGBX4, 0x000006ee);
// Enable DCLOCK
dispc_reg_out(VENC_DCLKCTL, VENC_DCKCTL_DCKEC);
// Set DCLOCK pattern
dispc_reg_out(VENC_DCLKPTN0, 1);
dispc_reg_out(VENC_DCLKPTN1, 0);
dispc_reg_out(VENC_DCLKPTN2, 0);
dispc_reg_out(VENC_DCLKPTN3, 0);
dispc_reg_out(VENC_DCLKPTN0A, 2);
dispc_reg_out(VENC_DCLKPTN1A, 0);
dispc_reg_out(VENC_DCLKPTN2A, 0);
dispc_reg_out(VENC_DCLKPTN3A, 0);
dispc_reg_out(VENC_DCLKHS, 0);
dispc_reg_out(VENC_DCLKHSA, 1);
dispc_reg_out(VENC_DCLKHR, 0);
dispc_reg_out(VENC_DCLKVS, 0);
dispc_reg_out(VENC_DCLKVR, 0);
// Enable LCD output control (accepting default polarity)
dispc_reg_out(VENC_LCDOUT, 0x1);
// Set brightness start position and pulse width to zero
dispc_reg_out(VENC_BRTS, 0);
dispc_reg_out(VENC_BRTW, 0);
// Set LCD AC toggle interval and horizontal position to zero
dispc_reg_out(VENC_ACCTL, 0);
// Set PWM period and width to zero
dispc_reg_out(VENC_PWMP, 0);
dispc_reg_out(VENC_PWMW, 0);
// Clear component and composite mode registers (applicable to
Analog DACS)
dispc_reg_out(VENC_CVBS, 0);
dispc_reg_out(VENC_CMPNT, 0);
// turning on horizontal and vertical syncs
dispc_reg_out(VENC_SYNCCTL, (VENC_SYNCCTL_SYEV|
VENC_SYNCCTL_SYEH) );
// Set OSD clock and OSD Sync Adavance registers
dispc_reg_out(VENC_OSDCLK0, 0);
dispc_reg_out(VENC_OSDCLK1, 1);
dispc_reg_out(VENC_OSDHAD, 0);
// Enable Video Window 0 / disable video window 1
dispc_reg_out(OSD_VIDWINMD, OSD_VIDWINMD_ACT0);
// Clear OSD Field Inversion for VID0 Use
dispc_reg_out(OSD_MODE, 0);
// Disable OSD0 Window
dispc_reg_out(OSD_OSDWIN0MD, 0x00002000);
// Disable OSD1 Window
dispc_reg_out(OSD_OSDWIN1MD, 0x00008000);
// set VPSS clock
dispc_reg_out(VPSS_CLKCTL, 0x0a);
}
else
{
/* Initialize the VPSS Clock Control register */
dispc_reg_out(VPSS_CLKCTL, 0x18);
// Set PINMUX0 reg to enable LCD (all other settings are
kept per u-boot)
dispc_reg_merge(PINMUX0, 0, PINMUX0_LOEEN);
dispc_reg_merge(PINMUX0, 0, PINMUX0_LFLDEN);
/* disable VCLK output pin enable */
dispc_reg_out(VENC_VIDCTL, 0x1101);
// Disable output sync pins
dispc_reg_out(VENC_SYNCCTL, 0 );
// Disable DCLOCK
dispc_reg_out(VENC_DCLKCTL, 0);
dispc_reg_out(VENC_DRGBX1, 0x0000057C);
// Disable LCD output control (accepting default polarity)
dispc_reg_out(VENC_LCDOUT, 0);
dispc_reg_out(VENC_CMPNT, 0x100);
// Enable Video Window 1 / disable video window 0
dispc_reg_out(OSD_VIDWINMD, 0x302);
// Enable OSD Field Inversion for VID1 Use
dispc_reg_out(OSD_MODE, 0x200);
// Disable OSD0 Window
dispc_reg_out(OSD_OSDWIN0MD, 0x00002003);
// Disable OSD1 Window
dispc_reg_out(OSD_OSDWIN1MD, 0x00008002);
// Set VID0 window origin and size
dispc_reg_out(OSD_VIDWIN0XP, 0);
dispc_reg_out(OSD_VIDWIN0YP, 0);
dispc_reg_out(OSD_VIDWIN0XL, 0x2d0);
dispc_reg_out(OSD_VIDWIN0YL, 0xf0);
// Set VID1 window origin and size
dispc_reg_out(OSD_VIDWIN1XP, 0);
dispc_reg_out(OSD_VIDWIN1YP, 0);
dispc_reg_out(OSD_VIDWIN1XL, 0x2d0);
dispc_reg_out(OSD_VIDWIN1YL, 0xf0);
// Set OSD0 window origin and size
dispc_reg_out(OSD_OSDWIN0XP, 0);
dispc_reg_out(OSD_OSDWIN0YP, 0);
dispc_reg_out(OSD_OSDWIN0XL, 0x2d0);
dispc_reg_out(OSD_OSDWIN0YL, 0xf0);
// Set OSD1 window origin and size
dispc_reg_out(OSD_OSDWIN1XP, 0);
dispc_reg_out(OSD_OSDWIN1YP, 0);
dispc_reg_out(OSD_OSDWIN1XL, 0x2d0);
dispc_reg_out(OSD_OSDWIN1YL, 0xf0);
// Set OSD1 window origin and size
dispc_reg_out(OSD_CURXP, 0);
dispc_reg_out(OSD_CURYP, 0);
dispc_reg_out(OSD_CURXL, 0x2d0);
dispc_reg_out(OSD_CURYL, 0xf0);
dispc_reg_out(VENC_HSPLS, 0);
dispc_reg_out(VENC_VSPLS, 0);
dispc_reg_out(VENC_HINT, 0);
dispc_reg_out(VENC_HSTART, 0);
dispc_reg_out(VENC_HVALID, 0);
dispc_reg_out(VENC_VINT, 0);
dispc_reg_out(VENC_VSTART, 0);
dispc_reg_out(VENC_VVALID, 0);
dispc_reg_out(VENC_HSDLY, 0);
dispc_reg_out(VENC_VSDLY, 0);
dispc_reg_out(VENC_YCCCTL, 0);
dispc_reg_out(VENC_VSTARTA, 0);
// Set OSD clock and OSD Sync Adavance registers
dispc_reg_out(VENC_OSDCLK0, 1);
dispc_reg_out(VENC_OSDCLK1, 2);
}
}
On Tue, 2008-05-06 at 08:24 +0200, Albert Burbea wrote:
> Hi
> a code example would be most welcome
> Albert
>
>
> On 5/6/08, steven.zhang <[EMAIL PROTECTED]> wrote:
>
> On Mon, 2008-05-05 at 10:20 -0700, Vim Venture wrote:
> > Welcome to the club, Steven. I'm working on the same thing.
> >
> > Some hints can be found in this list:
> >
>
> http://www.mail-archive.com/[email protected]/msg00605.html
> >
>
> http://www.mail-archive.com/[email protected]/msg01004.html
> >
> > Hope that helps a little...
> >
> > -Vim
> Thanks, Vim. I have successfully output the DC5 digital signal
> through.
> The hsync and vsync and vclk seems right.
> >
> > On May 4, 2008, at 2:33 AM, steven.zhang wrote:
> >
> > > Hi, all.
> > > I find that DC5 in EVM does not output any signal to drive
> the LCD.
> > > Does anyone know how to configure the Registers of VPBE
> subsystem?
> > > There are so many registers that drives me crazy.
> > > Thanks so much!
> > >
> > > _______________________________________________
> > > Davinci-linux-open-source mailing list
> > > [email protected]
> > >
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> [email protected]
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
>
>
> --
> Albert Burbea
> Harishonim 8
> Ramat Gan 52502, Israel
> Tel/Fax + 972-3-7526016
> Mobile: +972-52-3541842
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