Is these settings are for 8bit ITU BT 656 Embedded Sync?
________________________________ From: Stephen Berry [mailto:[EMAIL PROTECTED] Sent: Thursday, November 06, 2008 11:06 PM To: Prabhaharan R-TLS,Chennai Cc: Karicheri, Muralidharan; davinci-linux-open-source Subject: Re: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 Embedded Sync This is what I use to set up 656: /* * ======== setup656sync ======== */ /* This function will configure TVP5150 output data formatting */ static int setup656sync(tvp5150_params * tvp5150params) { int output1, output2, output4; int ret = 0; dev_dbg(tvp5150_i2c_dev, "\nStarting setup656sync..."); printk("\nStarting setup656sync..."); if ((tvp5150params->enablebt656sync) && (tvp5150params->data_width == TVP5150_WIDTH_8BIT)) { /* Configuration for 8-bit BT656 mode */ // BT656 has embedded syncs: 2:0='111' // extended code range bit 6 output1 = 0x47; // defaults for output pin muxing output4 = 0x08; output2 = 0x69; /* enable clock, enable Y[9:0] */ // also enables Hsync/Vsync bit2 printk("TVP5150 setting up BT656 - embedded sync codes.\n"); } else if ((!tvp5150params->enablebt656sync) && (tvp5150params->data_width == TVP5150_WIDTH_8BIT)) { /* Configuration for 8-bit seperate sync mode */ output1 = 0x40; output4 = 0x08; output2 = 0x6d; /* enable clock, enable Y[9:0] */ // also disables Hsync/Vsync bit2 printk("TVP5150 setting up ITU 601 - no sync codes.\n"); } else { return -EINVAL; } ret |= i2c_write_reg(&tvp5150_i2c_client, 0x27, 0x20); // mystery write ret |= i2c_write_reg(&tvp5150_i2c_client, TVP5150_VIDEO_STD, 0x0); ret |= i2c_write_reg(&tvp5150_i2c_client, TVP5150_DATA_RATE_SEL, output1); ret |= i2c_write_reg(&tvp5150_i2c_client, TVP5150_MISC_CTL, output2); ret |= i2c_write_reg(&tvp5150_i2c_client, TVP5150_CONF_SHARED_PIN, output4); dev_dbg(tvp5150_i2c_dev, "\nEnd of setup656sync..."); return ret; } Prabhaharan R-TLS,Chennai wrote: Hello Muralidharan, I am setting only two registers in the TVP5150 decoder. They are automask register to accept all the video inputs like NTSC, PAL etc. Then, I am setting the Miscellaneous controls register to enable Y Cb Cr output. Reg Address: 0x04 - val : 0x00 Reg Address: 0x03 - val: 0x09 I hope the other registers are setting to BT 656 Embedded Sync output by default. So, no need to set these registers again. Let me know, if I have to set anything else. Thanks, Prabhaharan.R ________________________________ From: Karicheri, Muralidharan [mailto:[EMAIL PROTECTED] Sent: Thursday, November 06, 2008 9:43 PM To: Prabhaharan R-TLS,Chennai; davinci-linux-open-source Subject: RE: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 Embedded Sync Check the response inline. ________________________________ From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Prabhaharan R-TLS,Chennai Sent: Thursday, November 06, 2008 9:59 AM To: davinci-linux-open-source Subject: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 Embedded Sync Importance: High Hello All, Currently I am working on the Video decoder driver for Davinci DMS 355. The driver is being implemented using the Montavista TI Linux code. We are using tvp5150 with 8-bit BT 656 embedded sync output. We have programmed the TVp5150 output as 8-bit embedded sync. We are getting the digital data, Y0 to Y7 and the pixel clock output from the TVp5150. It is feeding to the Dm355 as input. In order to implement this driver, we are using the TI TVP5146 and VPFE driver code as the base. For the VPFE side in the DM355, we are using the davinci_vpfe.c, davinci_vpfe.h, ccdc_dm355.c and ccdc_dm355.h files. We have not changed anything in the ccdc_dm355.c and .h. All the settings in the current code are same. Also, I have gone through the VPFE data sheet and identified the same settings in ccdc_dm355.c can be used as such. I did not find anything new for 8 bit BT 656 embedded sync. The current ccdc_dm355.c has been programmed for 8-bit YCbCr with separate sync. [MK] No. The ccdc_dm355.c has by default bt656 enabled (See the variable bt656_enable = 1) in ccdc ycbcr parameter structure. Make sure that the settings in tvp5150 is for BT656 embedded sync output. Following is the settings to check in your ccdc hardware by dumping the register values. For BT656, do the following setting REC656IF - enable R656ON and ECCFVH CCDCFG BW656 bit is reset MODESET, make sure following bit set INPMOD = 2 (YCbCr 8 - bit) PACK8 = 1 (pack to 8 bits) FLDMODE = 1 (interlaced) For Separate sync REC656IF - disable R656ON MODESET In addition to the values given above for BT656, set also FLDPOL, HDPOL & VDPOL to match with that of TVP. Also make sure VDHDOUT is reset We have used printk in all the driver functions and the tvp5150 related changes in the code is getting called properly. We have registered the VDINT0 interrupt in the vpfe code. But, the vpfe_isr is not getting called. It is registering properly and not getting failed. We don't know the reason for this. Is there any other setting required in the VPFE side for 8-bit BT 656 embedded sync other than mentioned in the hardware programming details of the VPFE CCDC part? If someone who worked on the tvp5150 and faced the same issue, please provide your valuable comments. Thanks a lot in advance. Regards, Prabhaharan.R DISCLAIMER: ------------------------------------------------------------------------ ----------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. It shall not attach any liability on the originator or HCL or its affiliates. Any views or opinions presented in this email are solely those of the author and may not necessarily reflect the opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of the author of this e-mail is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. 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