Hello Murali,
Please find the CCDC register settings for receiving and processing the 8-bit BT 656 Embedded Sync. Reading 0x3 to SYNCEN... Reading 0x2880 to MODESET... Reading 0x0 to HDWIDTH... Reading 0x0 to VDWIDTH... Reading 0x0 to PPLN... Reading 0x0 to LPFR... Reading 0x0 to SPH... Reading 0x59f to NPH... Reading 0x0 to SLV0... Reading 0x0 to SLV1... Reading 0xef to NLV... Reading 0xffff to CULH... Reading 0xff to CULV... Reading 0x2d to HSIZE... Reading 0x249 to SDOFST... Reading 0x3 to STADRH... Reading 0x8000 to STADRL... Reading 0x0 to CLAMP... Reading 0x0 to DCSUB... Reading 0x0 to COLPTN... Reading 0x0 to BLKCMP0... Reading 0x0 to BLKCMP1... Reading 0x0 to MEDFILT... Reading 0x80 to RYEGAIN... Reading 0x80 to GRCYGAIN... Reading 0x80 to GBGGAIN... Reading 0x80 to BMGGAIN... Reading 0x0 to OFFSET... Reading 0xfff to OUTCLIP... Reading 0x0 to VDINT0... Reading 0x0 to VDINT1... Reading 0x3 to REC656IF... Reading 0x8840 to CCDCFG... Let me know, if you need more info on the above. Still, the ISR for VDINT0 is not getting triggered. I had set the FLD POL, VD and HD POL as positive. Thanks, Prabha. ________________________________ From: Karicheri, Muralidharan [mailto:[EMAIL PROTECTED] Sent: Thursday, November 06, 2008 11:30 PM To: Prabhaharan R-TLS,Chennai; davinci-linux-open-source Subject: RE: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 EmbeddedSync Prabhakaran, You might want to check the tvp5150.c available in open source kernel tree. Also check your settings in TVP based on Stephen's email. I have not worked on TVP5150 and think it is similar to TVP5146. The dump of CCDC registers on your setup will help to determine if CCDC settings are correct or not. >> I will check the VD and HD POL for tvp5150 and VPFE. I think this will help as well. ________________________________ From: Prabhaharan R-TLS,Chennai [mailto:[EMAIL PROTECTED] Sent: Thursday, November 06, 2008 12:46 PM To: Karicheri, Muralidharan; davinci-linux-open-source Subject: RE: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 Embedded Sync Hello Murali, I used the tvp5146 code as reference for tvp5150. The I2C Communication is success from processor to tvp5150. I can able to read and write the I2C register settings. The default values read from the tvp5150 is same. Apart from these changes, I have set only two below (mail) mentioned registers. I will update you the register settings for CCDC by tomorrow. I will check the VD and HD POL for tvp5150 and VPFE. In case, if I want to call you, can I reach you by phone? Thanks, Prabha. ________________________________ From: Karicheri, Muralidharan [mailto:[EMAIL PROTECTED] Sent: Thursday, November 06, 2008 10:29 PM To: Prabhaharan R-TLS,Chennai; davinci-linux-open-source Subject: RE: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 Embedded Sync Did you develop the module TVP5150 from scratch or borrowed from open source? Also dump the ccdc registers and make sure the settings are as per my email below. Let me know once you confirm the ccdc settings are correct. Murali ________________________________ From: Prabhaharan R-TLS,Chennai [mailto:[EMAIL PROTECTED] Sent: Thursday, November 06, 2008 11:33 AM To: Karicheri, Muralidharan; davinci-linux-open-source Subject: RE: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 Embedded Sync Importance: High Hello Muralidharan, I am setting only two registers in the TVP5150 decoder. They are automask register to accept all the video inputs like NTSC, PAL etc. Then, I am setting the Miscellaneous controls register to enable Y Cb Cr output. Reg Address: 0x04 - val : 0x00 Reg Address: 0x03 - val: 0x09 I hope the other registers are setting to BT 656 Embedded Sync output by default. So, no need to set these registers again. Let me know, if I have to set anything else. Thanks, Prabhaharan.R ________________________________ From: Karicheri, Muralidharan [mailto:[EMAIL PROTECTED] Sent: Thursday, November 06, 2008 9:43 PM To: Prabhaharan R-TLS,Chennai; davinci-linux-open-source Subject: RE: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 Embedded Sync Check the response inline. ________________________________ From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Prabhaharan R-TLS,Chennai Sent: Thursday, November 06, 2008 9:59 AM To: davinci-linux-open-source Subject: Davinci DMS355 - Video Decoder TVP5150 8bit BT 656 Embedded Sync Importance: High Hello All, Currently I am working on the Video decoder driver for Davinci DMS 355. The driver is being implemented using the Montavista TI Linux code. We are using tvp5150 with 8-bit BT 656 embedded sync output. We have programmed the TVp5150 output as 8-bit embedded sync. We are getting the digital data, Y0 to Y7 and the pixel clock output from the TVp5150. It is feeding to the Dm355 as input. In order to implement this driver, we are using the TI TVP5146 and VPFE driver code as the base. For the VPFE side in the DM355, we are using the davinci_vpfe.c, davinci_vpfe.h, ccdc_dm355.c and ccdc_dm355.h files. We have not changed anything in the ccdc_dm355.c and .h. All the settings in the current code are same. Also, I have gone through the VPFE data sheet and identified the same settings in ccdc_dm355.c can be used as such. I did not find anything new for 8 bit BT 656 embedded sync. The current ccdc_dm355.c has been programmed for 8-bit YCbCr with separate sync. [MK] No. The ccdc_dm355.c has by default bt656 enabled (See the variable bt656_enable = 1) in ccdc ycbcr parameter structure. Make sure that the settings in tvp5150 is for BT656 embedded sync output. Following is the settings to check in your ccdc hardware by dumping the register values. For BT656, do the following setting REC656IF - enable R656ON and ECCFVH CCDCFG BW656 bit is reset MODESET, make sure following bit set INPMOD = 2 (YCbCr 8 - bit) PACK8 = 1 (pack to 8 bits) FLDMODE = 1 (interlaced) For Separate sync REC656IF - disable R656ON MODESET In addition to the values given above for BT656, set also FLDPOL, HDPOL & VDPOL to match with that of TVP. Also make sure VDHDOUT is reset We have used printk in all the driver functions and the tvp5150 related changes in the code is getting called properly. We have registered the VDINT0 interrupt in the vpfe code. But, the vpfe_isr is not getting called. It is registering properly and not getting failed. We don't know the reason for this. Is there any other setting required in the VPFE side for 8-bit BT 656 embedded sync other than mentioned in the hardware programming details of the VPFE CCDC part? If someone who worked on the tvp5150 and faced the same issue, please provide your valuable comments. Thanks a lot in advance. Regards, Prabhaharan.R DISCLAIMER: ------------------------------------------------------------------------ ----------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. It shall not attach any liability on the originator or HCL or its affiliates. Any views or opinions presented in this email are solely those of the author and may not necessarily reflect the opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of the author of this e-mail is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. 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