Hugo Villeneuve <[EMAIL PROTECTED]> writes:
> The Lyrtech SFFSDR (Small form Factor Software Defined Radio) board
> is built around a TI DM6446 and a Xilinx Virtex-4 (SX-35) FPGA. This
> patch adds board setup code for the SFFSDR and a device driver for
> the Virtex-4 FPGA.
>
> Signed-off-by: Hugo Villeneuve <[EMAIL PROTECTED]>
> ---
> arch/arm/mach-davinci/Kconfig | 23 ++
> arch/arm/mach-davinci/Makefile | 2 +
> arch/arm/mach-davinci/board-sffsdr.c | 223 +++++++++++++
> arch/arm/mach-davinci/sffsdr-fpga.c | 501
> +++++++++++++++++++++++++++++
> include/asm-arm/plat-sffsdr/sffsdr-fpga.h | 30 ++
Please separate out the FPGA-related stuff into a separate patch. Lets
get the basic board support in first. The FPGA support is going to
have to take a different path to mainline.
Kevin
> 5 files changed, 779 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-davinci/board-sffsdr.c
> create mode 100644 arch/arm/mach-davinci/sffsdr-fpga.c
> create mode 100644 include/asm-arm/plat-sffsdr/sffsdr-fpga.h
>
> diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
> index 43b6359..0f46228 100644
> --- a/arch/arm/mach-davinci/Kconfig
> +++ b/arch/arm/mach-davinci/Kconfig
> @@ -42,6 +42,29 @@ config MACH_DAVINCI_DM355_EVM
> Configure this option to specify the whether the board used
> for development is a DM355 EVM
>
> +config MACH_DAVINCI_SFFSDR
> + bool "Lyrtech SFFSDR"
> + default n
> + depends on ARCH_DAVINCI_DM644x
> + help
> + Say Y here to select the Lyrtech Small Form Factor
> + Software Defined Radio (SFFSDR) board.
> +
> +config SFFSDR_FPGA
> + tristate "SFFSDR SX-35 FPGA support"
> + default n
> + depends on MACH_DAVINCI_SFFSDR
> + select FPGALOAD
> + select FW_LOADER
> + help
> + This driver supports the SX-35 FPGA on the Lyrtech SFFSDR board.
> + Amongst other things, the FPGA is used to generate the clocks
> + for the audio codec and for transferring data to/from the other
> + stacked boards (using the EMIF or VPSS ports).
> +
> + To compile this driver as module, choose M here: the
> + module will be called sffsdr-fpga.
> +
> config DAVINCI_RESET_CLOCKS
> bool "Reset unused clocks during boot"
> depends on ARCH_DAVINCI
> diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
> index 420a33e..8478220 100644
> --- a/arch/arm/mach-davinci/Makefile
> +++ b/arch/arm/mach-davinci/Makefile
> @@ -11,3 +11,5 @@ obj-y := time.o irq.o clock.o
> serial.o io.o id.o psc.o \
> obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
> obj-$(CONFIG_MACH_DAVINCI_DM646X_EVM) += board-dm646x-evm.o
> obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
> +obj-$(CONFIG_MACH_DAVINCI_SFFSDR) += board-sffsdr.o
> +obj-$(CONFIG_SFFSDR_FPGA) += sffsdr-fpga.o
> diff --git a/arch/arm/mach-davinci/board-sffsdr.c
> b/arch/arm/mach-davinci/board-sffsdr.c
> new file mode 100644
> index 0000000..0b03ce5
> --- /dev/null
> +++ b/arch/arm/mach-davinci/board-sffsdr.c
> @@ -0,0 +1,223 @@
> +/*
> + * Lyrtech SFFSDR board support.
> + *
> + * Copyright (C) 2008 Philip Balister, OpenSDR <[EMAIL PROTECTED]>
> + * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
> + *
> + * Based on DV-EVM platform, original copyright follows:
> + *
> + * Copyright (C) 2007 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +
> +#include <linux/i2c.h>
> +#include <linux/i2c/at24.h>
> +#include <linux/etherdevice.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/mtd/physmap.h>
> +#include <linux/io.h>
> +
> +#include <asm/setup.h>
> +#include <asm/mach-types.h>
> +
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +#include <asm/mach/flash.h>
> +
> +#include <mach/dm644x.h>
> +#include <mach/common.h>
> +#include <mach/board.h>
> +#include <mach/emac.h>
> +#include <mach/i2c.h>
> +#include <mach/serial.h>
> +#include <mach/psc.h>
> +
> +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
> +
> +struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
> + /* U-Boot Environment: Block 0
> + * UBL: Block 1
> + * U-Boot: Blocks 6-7 (256 kb)
> + * Integrity Kernel: Blocks 8-31 (3 Mb)
> + * Integrity Data: Blocks 100-END
> + */
> + {
> + .name = "Linux Kernel",
> + .offset = 32 * SZ_128K,
> + .size = 16 * SZ_128K, /* 2 Mb */
> + .mask_flags = MTD_WRITEABLE, /* Force read-only */
> + },
> + {
> + .name = "Linux ROOT",
> + .offset = MTDPART_OFS_APPEND,
> + .size = 256 * SZ_128K, /* 32 Mb */
> + .mask_flags = 0, /* R/W */
> + },
> +};
> +
> +static struct flash_platform_data davinci_sffsdr_nandflash_data = {
> + .parts = davinci_sffsdr_nandflash_partition,
> + .nr_parts = ARRAY_SIZE(davinci_sffsdr_nandflash_partition),
> +};
> +
> +static struct resource davinci_sffsdr_nandflash_resource = {
> + .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
> + .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
> + .flags = IORESOURCE_MEM,
> +};
> +
> +static struct platform_device davinci_sffsdr_nandflash_device = {
> + .name = "davinci_nand", /* Name of driver */
> + .id = 0,
> + .dev = {
> + .platform_data = &davinci_sffsdr_nandflash_data,
> + },
> + .num_resources = 1,
> + .resource = &davinci_sffsdr_nandflash_resource,
> +};
> +
> +/* Get Ethernet address from kernel boot params */
> +static u8 davinci_sffsdr_mac_addr[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
> +
> +static struct at24_platform_data eeprom_info = {
> + .byte_len = (64*1024) / 8,
> + .page_size = 32,
> + .flags = AT24_FLAG_ADDR16,
> +};
> +
> +static struct i2c_board_info __initdata i2c_info[] = {
> + {
> + I2C_BOARD_INFO("24lc64", 0x50),
> + .platform_data = &eeprom_info,
> + },
> + /* Other I2C devices:
> + * MSP430, addr 0x23 (not used)
> + * PCA9543, addr 0x70 (setup done by U-Boot)
> + * ADS7828, addr 0x48 (ADC for voltage monitoring.)
> + */
> +};
> +
> +static struct davinci_i2c_platform_data i2c_pdata = {
> + .bus_freq = 20 /* kHz */,
> + .bus_delay = 100 /* usec */,
> +};
> +
> +static void __init sffsdr_init_i2c(void)
> +{
> + davinci_init_i2c(&i2c_pdata);
> + i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
> +}
> +
> +/* FPGA physical EMIF register resources. */
> +static struct resource davinci_sffsdr_fpga_resources[] = {
> + {
> + .name = "selectmap",
> + .start = 0x4000000,
> + .end = 0x4000003, /* 4 bytes */
> + .flags = IORESOURCE_MEM,
> + },
> + {
> + .name = "fpgaregs",
> + .start = 0x4008000,
> + .end = 0x4008FFF, /* 1 kbytes */
> + .flags = IORESOURCE_MEM,
> + },
> +};
> +
> +static struct platform_device davinci_sffsdr_fpga_device = {
> + .name = "sffsdr-fpga", /* Name of driver */
> + .id = 0,
> + .dev = {
> + .platform_data = &davinci_sffsdr_fpga_resources,
> + },
> + .num_resources = ARRAY_SIZE(davinci_sffsdr_fpga_resources),
> + .resource = davinci_sffsdr_fpga_resources,
> +};
> +
> +static struct platform_device *davinci_sffsdr_devices[] __initdata = {
> + &davinci_sffsdr_nandflash_device,
> + &davinci_sffsdr_fpga_device,
> +};
> +
> +static struct davinci_uart_config davinci_sffsdr_uart_config __initdata = {
> + .enabled_uarts = (1 << 0),
> +};
> +
> +static struct davinci_board_config_kernel davinci_sffsdr_config[] __initdata
> = {
> + { DAVINCI_TAG_UART, &davinci_sffsdr_uart_config },
> +};
> +
> +static void __init davinci_sffsdr_map_io(void)
> +{
> + davinci_map_common_io();
> +}
> +
> +static __init void davinci_sffsdr_init(void)
> +{
> + davinci_psc_init();
> + platform_add_devices(davinci_sffsdr_devices,
> + ARRAY_SIZE(davinci_sffsdr_devices));
> + sffsdr_init_i2c();
> + davinci_board_config = davinci_sffsdr_config;
> + davinci_board_config_size = ARRAY_SIZE(davinci_sffsdr_config);
> + davinci_serial_init();
> + davinci_init_emac(davinci_sffsdr_mac_addr);
> + setup_usb(0, 0); /* We support only peripheral mode. */
> +}
> +
> +static int davinci_cpmac_eth_setup(char *str)
> +{
> + int i;
> +
> + if (str == NULL)
> + return 0;
> +
> + /* Conversion of a MAC address from a string (AA:BB:CC:DD:EE:FF)
> + * to a 6 bytes array. */
> + for (i = 0; i < 6; i++)
> + davinci_sffsdr_mac_addr[i] = simple_strtol(&str[i*3],
> + (char **)NULL, 16);
> +
> + return 1;
> +}
> +/* Get MAC address from kernel boot parameter eth=AA:BB:CC:DD:EE:FF */
> +__setup("eth=", davinci_cpmac_eth_setup);
> +
> +static __init void davinci_sffsdr_irq_init(void)
> +{
> + davinci_init_common_hw();
> + davinci_irq_init();
> +}
> +
> +MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
> + /* Maintainer: Hugo Villeneuve [EMAIL PROTECTED] */
> + .phys_io = IO_PHYS,
> + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
> + .boot_params = (DAVINCI_DDR_BASE + 0x100),
> + .map_io = davinci_sffsdr_map_io,
> + .init_irq = davinci_sffsdr_irq_init,
> + .timer = &davinci_timer,
> + .init_machine = davinci_sffsdr_init,
> +MACHINE_END
> diff --git a/arch/arm/mach-davinci/sffsdr-fpga.c
> b/arch/arm/mach-davinci/sffsdr-fpga.c
> new file mode 100644
> index 0000000..8b7030f
> --- /dev/null
> +++ b/arch/arm/mach-davinci/sffsdr-fpga.c
> @@ -0,0 +1,501 @@
> +/*
> + * SFFSDR-board specific FPGA driver
> + *
> + * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
> + *
> + * The FPGA is loaded using the SelectMAP mode through
> + * the EMIF interface and some dedicated control signals:
> + *
> + * FPGA DM6446
> + * --------------------
> + * PROGRAM_B GPIO37
> + * DONE GPIO39
> + * INIT GPIO40
> + * DOUT_BUSY GPIO42 (Not used)
> + * CS_B EMIF_A13 OR CS3n
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/device.h>
> +#include <linux/string.h>
> +#include <linux/platform_device.h>
> +#include <linux/err.h>
> +#include <linux/firmware.h>
> +#include <linux/io.h>
> +#include <linux/cdev.h>
> +#include <linux/fpgaload.h>
> +#include <linux/fs.h>
> +
> +#include <asm/uaccess.h>
> +#include <asm/gpio.h>
> +
> +#define MODULE_NAME "sffsdr-fpga"
> +
> +/* Define this to have verbose debug messages. */
> +#define SFFSDR_FPGA_DEBUG 1
> +
> +#define XC4VSX35_PAYLOAD_SIZE (1707240)
> +
> +#ifdef SFFSDR_FPGA_DEBUG
> +#define DBGMSG(fmt, args...) \
> + printk(KERN_INFO "%s: "fmt"\n" , MODULE_NAME, ## args)
> +#define FAILMSG(fmt, args...) \
> + printk(KERN_ERR "%s: "fmt"\n" , MODULE_NAME, ## args)
> +#else
> +#define DBGMSG(fmt, args...)
> +#define FAILMSG(fmt, args...)
> +#endif
> +
> +/* Lyrtech specific register inside FPGA, accessed through EMIF. */
> +#define FPGA_REVISION_REG_OFFSET (0x000 / 4)
> +#define FPGA_GLOBAL_CTRL_REG_OFFSET (0x040 / 4)
> +#define FPGA_LED_CONTROL_REG_OFFSET (0x300 / 4)
> +#define FPGA_PLL_CODEC_REG_OFFSET (0x800 / 4)
> +
> +#define FPGA_FULL_RESET_VAL 3
> +#define FPGA_PARTIAL_RESET_VAL 2
> +
> +#define FPGA_DS2_ON (1<<0)
> +#define FPGA_DS3_ON (1<<1)
> +#define FPGA_DS4_ON (1<<2)
> +#define FPGA_DS5_ON (1<<3)
> +#define FPGA_DS6_ON (1<<4)
> +
> +/* Sampling frequency divider, bits 5:4 */
> +#define FPGA_FS_DIV_BY_1 (0<<4)
> +#define FPGA_FS_DIV_BY_2 (1<<4)
> +#define FPGA_FS_DIV_BY_4 (2<<4)
> +#define FPGA_FS_DIV_RSV (3<<4)
> +
> +/* Sampling rate selection, bit 2 */
> +#define FPGA_SR_STANDARD (0<<2) /* Standard sampling rate, default */
> +#define FPGA_SR_DOUBLE (1<<2) /* Double sampling rate */
> +
> +/* Sampling frequency selection, bits 1:0 */
> +#define FPGA_FS_48000 (0<<0) /* 48.0 kHz (PLL 12.288 MHz) */
> +#define FPGA_FS_44100 (1<<0) /* 44.1 kHz (PLL 11.2896 MHz) */
> +#define FPGA_FS_32000 (2<<0) /* 32.0 kHz (PLL 8.192 MHz) */
> +#define FPGA_FS_RSV (3<<0) /* Reserved */
> +
> +static const char sffsdr_fpga_device_name[] = "sffsdr-fpga";
> +/* in /lib/firmware */
> +static const char sffsdr_fpga_bitstream_name[] = "sffsdr_sx35.bit";
> +
> +struct sffsdr_fpga_dev {
> + const char *bitstream_name;
> + u8 *bitstream_data;
> + size_t bitstream_length;
> + size_t bitstream_max_size;
> + dev_t cdevno;
> + struct cdev cdev; /* Char device structure */
> +};
> +
> +static enum {
> + SFFSDR_FPGA_INIT_HAVE_MEM,
> + SFFSDR_FPGA_INIT_HAVE_SELECTMAP_MMIO,
> + SFFSDR_FPGA_INIT_HAVE_FPGAREGS_MMIO,
> + SFFSDR_FPGA_INIT_CHAR_DEV_REGISTERED,
> + SFFSDR_FPGA_INIT_FPGA_DEV_REGISTERED,
> + SFFSDR_FPGA_INIT_FPGA_BITSTREAM_LOADED,
> +} sffsdr_fpga_init_state;
> +
> +static u8 *selectmap;
> +static u32 *fpgaregs;
> +
> +/* Reset the inside logic of the FPGA according to the
> + * bitstream mode. This is done when the bitstream has
> + * been programmed and is Lyrtech SFF-SDR specific. */
> +static void sffsdr_fpga_reset(int bitstream_mode)
> +{
> + u32 value;
> +
> + if (bitstream_mode == BITSTREAM_MODE_FULL)
> + value = FPGA_FULL_RESET_VAL;
> + else
> + value = FPGA_PARTIAL_RESET_VAL;
> +
> + fpgaregs[FPGA_GLOBAL_CTRL_REG_OFFSET] = value;
> + fpgaregs[FPGA_GLOBAL_CTRL_REG_OFFSET] = 0;
> +}
> +
> +static int sffsdr_fpga_post_load(int bitstream_mode)
> +{
> + DBGMSG("sffsdr_fpga_post_load()");
> +
> + sffsdr_fpga_reset(bitstream_mode);
> +
> + DBGMSG("FPGA Revision: %d",
> + fpgaregs[FPGA_REVISION_REG_OFFSET] & 0x0000FFFF);
> +
> + /* Light LED DS2 to indicate success. */
> + fpgaregs[FPGA_LED_CONTROL_REG_OFFSET] = FPGA_DS2_ON;
> +
> + /* Set default CODEC clock values. */
> + fpgaregs[FPGA_PLL_CODEC_REG_OFFSET] =
> + FPGA_FS_DIV_BY_1 | FPGA_FS_44100 | FPGA_SR_STANDARD;
> +
> + sffsdr_fpga_init_state = SFFSDR_FPGA_INIT_FPGA_BITSTREAM_LOADED;
> +
> + return 0;
> +}
> +
> +/* Swap bits inside a byte. */
> +static u8 swapbits(u8 c)
> +{
> + int i;
> + u8 result = 0;
> +
> + for (i = 0; i < 8; ++i) {
> + result = result << 1;
> + result |= (c & 1);
> + c = c >> 1;
> + }
> +
> + return result;
> +}
> +
> +/*
> + * Writes a byte of data to the FPGA using the SelectMAP
> + * interface. The FPGA_SELECT_MAP_REG address is within
> + * the FPGA address space (CS3), and when we write a byte
> + * to that address, the CCLK line will be toggled.
> + */
> +static int sffsdr_fpga_write_byte(u8 *data, int size)
> +{
> + int k;
> +
> + for (k = 0; k < size; k++)
> + selectmap[0] = swapbits(data[k]);
> +
> + return 0;
> +}
> +
> +static const struct fpgaload_t fpgaload = {
> + .fpga_family = FPGA_FAMILY_XILINX_XC4V,
> + .payload_full_size = XC4VSX35_PAYLOAD_SIZE,
> + .program_b = GPIO(37),
> + .done = GPIO(39),
> + .init_b = GPIO(40),
> + .write_byte = sffsdr_fpga_write_byte,
> +};
> +
> +static int sffsdr_fpga_bitstream_load(const u8 *data, size_t size)
> +{
> + int retval;
> + int bitstream_mode;
> +
> + DBGMSG("Programming bitstream");
> + DBGMSG(" File size = %d kb", size / 1024);
> +
> + sffsdr_fpga_init_state = SFFSDR_FPGA_INIT_FPGA_DEV_REGISTERED;
> +
> + retval = fpgaload_bitstream_load(&fpgaload, data, size,
> + &bitstream_mode);
> + if (retval < 0)
> + FAILMSG("Error, firmware not loaded in FPGA");
> + else
> + retval = sffsdr_fpga_post_load(bitstream_mode);
> +
> + return retval;
> +}
> +
> +/* Open method.
> + *
> + * return value:
> + * 0 in case of success
> + * -ENOMEM if unable to allocate memory.
> + */
> +int sffsdr_fpga_open(struct inode *inode, struct file *filp)
> +{
> + struct sffsdr_fpga_dev *dev;
> +
> + DBGMSG("sffsdr_fpga_open()");
> +
> + dev = container_of(inode->i_cdev, struct sffsdr_fpga_dev, cdev);
> + filp->private_data = dev; /* for other methods */
> +
> + dev->bitstream_length = 0;
> + dev->bitstream_data = kmalloc(dev->bitstream_max_size,
> + GFP_KERNEL);
> + if (!dev->bitstream_data) {
> + FAILMSG("Failed to allocate memory for bitstream");
> + return -ENOMEM;
> + }
> +
> + return 0; /* success */
> +}
> +
> +/* Write method. Fill buffer with bitstream data. */
> +ssize_t sffsdr_fpga_write(struct file *filp, const char __user *buff,
> + size_t count, loff_t *offp)
> +{
> + struct sffsdr_fpga_dev *dev =
> + (struct sffsdr_fpga_dev *) filp->private_data;
> +
> + if ((dev->bitstream_length + count) >= dev->bitstream_max_size) {
> + FAILMSG("Bitstream buffer size exceeded");
> + return -EFBIG;
> + }
> +
> + if (copy_from_user(dev->bitstream_data + dev->bitstream_length,
> + (void __user *) buff, count))
> + return -EFAULT;
> +
> + dev->bitstream_length += count;
> +
> + return count;
> +}
> +
> +/* Release method. This will initiate the FPGA programming. */
> +int sffsdr_fpga_release(struct inode *inode, struct file *filp)
> +{
> + int retval;
> + struct sffsdr_fpga_dev *dev =
> + (struct sffsdr_fpga_dev *) filp->private_data;
> +
> + if (!dev->bitstream_data)
> + return -EFAULT;
> +
> + retval = sffsdr_fpga_bitstream_load(dev->bitstream_data,
> + dev->bitstream_length);
> + kfree(dev->bitstream_data);
> +
> + return retval;
> +}
> +
> +static struct file_operations sffsdr_fpga_fops = {
> + .owner = THIS_MODULE,
> + .open = sffsdr_fpga_open,
> + .write = sffsdr_fpga_write,
> + .release = sffsdr_fpga_release
> +};
> +
> +int sffsdr_fpga_set_codec_fs(int fs)
> +{
> + u32 fs_mask;
> +
> + if (sffsdr_fpga_init_state != SFFSDR_FPGA_INIT_FPGA_BITSTREAM_LOADED) {
> + FAILMSG("FPGA is not programmed");
> + return -ENODEV;
> + }
> +
> + switch (fs) {
> + case 32000:
> + fs_mask = FPGA_FS_32000;
> + break;
> + case 44100:
> + fs_mask = FPGA_FS_44100;
> + break;
> + case 48000:
> + fs_mask = FPGA_FS_48000;
> + break;
> + default:
> + FAILMSG("Unsupported sampling frequency");
> + return -EFAULT;
> + break;
> + }
> +
> + fpgaregs[FPGA_PLL_CODEC_REG_OFFSET] =
> + FPGA_FS_DIV_BY_1 | fs_mask | FPGA_SR_STANDARD;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(sffsdr_fpga_set_codec_fs);
> +
> +static int sffsdr_fpga_setup_cdev(struct sffsdr_fpga_dev *dev)
> +{
> + const int sffsdr_fpga_minor = 0;
> + int result;
> +
> + /* Dynamic major */
> + result = alloc_chrdev_region(&dev->cdevno, sffsdr_fpga_minor, 1,
> + sffsdr_fpga_device_name);
> + if (result < 0) {
> + FAILMSG("Can't get major");
> + return result;
> + }
> +
> + cdev_init(&dev->cdev, &sffsdr_fpga_fops);
> + dev->cdev.owner = THIS_MODULE;
> + dev->cdev.ops = &sffsdr_fpga_fops;
> +
> + result = cdev_add(&dev->cdev, dev->cdevno, 1);
> + if (result)
> + FAILMSG("Error %d registering char driver", result);
> +
> + return result;
> +}
> +
> +static void sffsdr_fpga_cleanup(struct sffsdr_fpga_dev *dev)
> +{
> + if (!dev)
> + return;
> +
> + switch (sffsdr_fpga_init_state) {
> + case SFFSDR_FPGA_INIT_FPGA_BITSTREAM_LOADED:
> + /* Nothing to do. */
> + case SFFSDR_FPGA_INIT_FPGA_DEV_REGISTERED:
> + fpgaload_unregister(&fpgaload);
> + case SFFSDR_FPGA_INIT_CHAR_DEV_REGISTERED:
> + unregister_chrdev_region(dev->cdevno, 1);
> + cdev_del(&dev->cdev);
> + case SFFSDR_FPGA_INIT_HAVE_FPGAREGS_MMIO:
> + iounmap(fpgaregs);
> + case SFFSDR_FPGA_INIT_HAVE_SELECTMAP_MMIO:
> + iounmap(selectmap);
> + case SFFSDR_FPGA_INIT_HAVE_MEM:
> + kfree(dev);
> + }
> +}
> +
> +int __init sffsdr_fpga_probe(struct platform_device *pdev)
> +{
> + struct sffsdr_fpga_dev *dev;
> + struct resource *selectmap_res;
> + struct resource *fpgaregs_res;
> + const struct firmware *fw_entry;
> + int len;
> + int result;
> +
> + DBGMSG("sffsdr_fpga_probe()");
> +
> + dev = kzalloc(sizeof(*dev), GFP_KERNEL);
> + if (!dev) {
> + FAILMSG("Failed to allocate device structure");
> + result = -ENOMEM;
> + goto error;
> + }
> + sffsdr_fpga_init_state = SFFSDR_FPGA_INIT_HAVE_MEM;
> + pdev->dev.driver_data = dev; /* Private driver data */
> + dev->bitstream_max_size = XC4VSX35_PAYLOAD_SIZE + 10240;
> + dev->bitstream_name = sffsdr_fpga_bitstream_name;
> +
> + /* Assign virtual addresses to SELECTMAP I/O memory regions. */
> + selectmap_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> + "selectmap");
> + if (!selectmap_res) {
> + FAILMSG("Error getting selectmap ressource");
> + result = -ENODEV;
> + goto error;
> + }
> + len = selectmap_res->end - selectmap_res->start;
> + selectmap = ioremap(selectmap_res->start, len);
> + if (!selectmap) {
> + FAILMSG("Can't remap selectmap register");
> + result = -ENXIO;
> + goto error;
> + }
> + sffsdr_fpga_init_state = SFFSDR_FPGA_INIT_HAVE_SELECTMAP_MMIO;
> +
> + /* Assign virtual addresses to FPGAREGS I/O memory regions. */
> + fpgaregs_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> + "fpgaregs");
> + if (!fpgaregs_res) {
> + FAILMSG("Error getting fpgaregs ressource");
> + result = -ENODEV;
> + goto error;
> + }
> + len = fpgaregs_res->end - fpgaregs_res->start;
> + fpgaregs = ioremap(fpgaregs_res->start, len);
> + if (!fpgaregs) {
> + FAILMSG("Can't remap fpgaregs registers");
> + result = -ENXIO;
> + goto error;
> + }
> + sffsdr_fpga_init_state = SFFSDR_FPGA_INIT_HAVE_FPGAREGS_MMIO;
> +
> + result = sffsdr_fpga_setup_cdev(dev);
> + if (result < 0) {
> + FAILMSG("Error registering char driver");
> + goto error;
> + }
> + sffsdr_fpga_init_state = SFFSDR_FPGA_INIT_CHAR_DEV_REGISTERED;
> +
> + result = fpgaload_register(&fpgaload);
> + if (result < 0) {
> + FAILMSG("Error registering fpgaload driver");
> + goto error;
> + }
> + sffsdr_fpga_init_state = SFFSDR_FPGA_INIT_FPGA_DEV_REGISTERED;
> +
> + /* Try to load firmware through hotplug if available. */
> + result = request_firmware(&fw_entry, dev->bitstream_name,
> + &pdev->dev);
> + if (result < 0) {
> + /* Not an error preventing the driver from being loaded. */
> + result = 0;
> + DBGMSG("Firmware not available");
> + } else {
> + result = sffsdr_fpga_bitstream_load(fw_entry->data,
> + fw_entry->size);
> + release_firmware(fw_entry);
> + }
> +
> + return result;
> +
> +error:
> + sffsdr_fpga_cleanup(dev);
> + return result;
> +}
> +
> +static int __devexit sffsdr_fpga_remove(struct platform_device *pdev)
> +{
> + struct sffsdr_fpga_dev *dev = platform_get_drvdata(pdev);
> +
> + DBGMSG("sffsdr_fpga_remove()");
> + sffsdr_fpga_cleanup(dev);
> +
> + return 0;
> +}
> +
> +static struct platform_driver sffsdr_fpga_platform_driver = {
> + .driver = {
> + .name = MODULE_NAME,
> + .owner = THIS_MODULE,
> + },
> + .remove = sffsdr_fpga_remove,
> +};
> +
> +int __init sffsdr_fpga_init(void)
> +{
> + int res;
> +
> + DBGMSG("sffsdr_fpga_init()");
> +
> + res = platform_driver_probe(&sffsdr_fpga_platform_driver,
> + sffsdr_fpga_probe);
> + if (res) {
> + DBGMSG("platform_driver_probe() failed");
> + return res;
> + }
> +
> + return 0;
> +}
> +module_init(sffsdr_fpga_init);
> +
> +void __exit sffsdr_fpga_exit(void)
> +{
> + DBGMSG("sffsdr_fpga_exit()");
> + platform_driver_unregister(&sffsdr_fpga_platform_driver);
> +}
> +module_exit(sffsdr_fpga_exit);
> +
> +MODULE_AUTHOR("Hugo Villeneuve <[EMAIL PROTECTED]>");
> +MODULE_DESCRIPTION("Lyrtech SFFSDR SX-35 FPGA driver");
> +MODULE_LICENSE("GPL");
> diff --git a/include/asm-arm/plat-sffsdr/sffsdr-fpga.h
> b/include/asm-arm/plat-sffsdr/sffsdr-fpga.h
> new file mode 100644
> index 0000000..74fc537
> --- /dev/null
> +++ b/include/asm-arm/plat-sffsdr/sffsdr-fpga.h
> @@ -0,0 +1,30 @@
> +/*
> + * sffsdr_fpga0.h
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
> + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
> + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
> + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef __SFFSDR_FPGA0_H
> +#define __SFFSDR_FPGA0_H
> +
> +int sffsdr_fpga_set_codec_fs(int fs);
> +
> +#endif /* __SFFSDR_FPGA0_H */
> --
> 1.5.5
>
>
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