David Brownell wrote:
> /* NOTE: we never transfer more than rw_threshold bytes
> - * to/from the fifo here; there's no I/O overlap.
> + * to/from the fifo here; there's no I/O overlap. We don't
> + * try to speed up PIO by using 32 bit FIFO writes.
> */
> - if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
> - DAVINCI_MMCSD_WRITE_FIFO(p, host->base, n);
> - } else {
> - DAVINCI_MMCSD_READ_FIFO(p, host->base, n);
> - }
> + if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
> + iowrite8_rep(host->base + DAVINCI_MMCDXR, p, n);
> + else
> + ioread8_rep(host->base + DAVINCI_MMCDXR, p, n);
> host->buffer = p;
> }
>
Are you sure this works? MMCFIFOCTL has a field "ACCWD" which
determines the CPU/EDMA fifo access width. I would call the 32 bit rep
routine followed by 1 more 32 bit write if a non-multiple of 4 was
given.
Troy
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