On Wednesday 04 February 2009, Troy Kisky wrote:
> >
> > Can't use io{read,write}32_rep() without knowing (a) that "p"
> > is aligned on a 32-bit boundary, (b) that "n" is a multiple of
> > four bytes. In the same way, the current ASM code seems buggy
> > since it assumes that "p" is 16-bit aligned.
> >
> > - Dave
> >
> >
> If that's the case, then
I'll let this be dealt with as part of merge-to-mainline. :)
My two cents is that there's no point to spending time
to speed up PIO. Outside of card enumeration, and maybe
sending card unlock passwords, it shouldn't be used. DMA
will kick in on all performance-critical code paths; and
if it can't, that'd be a priority bug.
- Dave
> static inline iowrite8_32_align_rep(void __iomem *fifo, u8 *p, int n)
> {
> if (((int)p) & 3) {
> int align_cnt = 4 -(((int)p) & 3);
> if (align_cnt > n) align_cnt = n;
> iowrite8_rep(fifo, p, align_cnt);
> p += align_cnt;
> n -= align_cnt;
> }
> if (n>>2) {
> iowrite32_rep(fifo, p, n>>2);
> p += n & ~3;
> n &= 3;
> }
> if (n)
> iowrite8_rep(fifo, p, n);
> }
>
>
> The old bounce buffers probably guaranteed alignment before.
>
> Troy
>
>
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