Overview - distinguish between PLL1- and PLL2-derived SYSCLKs - PLL-derived AUX ans bypass clocks are sourced before the multiplier and divider(s) - multiple tweaks and updates from David Brownell (thanks!)
Notes: - boot-tested on dm6446, dm355, dm6467 Signed-off-by: Kevin Hilman <[email protected]> --- arch/arm/mach-davinci/board-dm355-evm.c | 7 ++ arch/arm/mach-davinci/board-dm644x-evm.c | 2 +- arch/arm/mach-davinci/clock.c | 28 ++++-- arch/arm/mach-davinci/clock.h | 3 +- arch/arm/mach-davinci/dm355.c | 168 ++++++++++++++++++------------ arch/arm/mach-davinci/dm644x.c | 160 +++++++++++++++++++++------- arch/arm/mach-davinci/dm646x.c | 130 ++++++++++++++--------- arch/arm/mach-davinci/psc.c | 4 - drivers/mtd/nand/davinci_nand.c | 7 +- 9 files changed, 335 insertions(+), 174 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index f477933..8a0359e 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -19,6 +19,7 @@ #include <linux/i2c.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/clk.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -225,10 +226,16 @@ static struct davinci_mmc_config dm355evm_mmc_config = { static __init void dm355_evm_init(void) { + struct clk *aemif; + gpio_request(1, "dm9000"); gpio_direction_input(1); dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); + aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); + clk_enable(aemif); + clk_put(aemif); + platform_add_devices(davinci_evm_devices, ARRAY_SIZE(davinci_evm_devices)); evm_init_i2c(); diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 0c98674..53444f7 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -672,7 +672,7 @@ static __init void davinci_evm_irq_init(void) davinci_irq_init(); } -MACHINE_START(DAVINCI_EVM, "DaVinci EVM") +MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") /* Maintainer: MontaVista Software <[email protected]> */ .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index cddd06b..c095f70 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -230,7 +230,7 @@ int clk_register(struct clk *clk) if (clk->rate) return 0; - /* Otherwise, use parent rate and any divider */ + /* Otherwise, default to parent rate */ if (clk->parent) clk->rate = clk->parent->rate; @@ -278,17 +278,28 @@ static void clk_sysclk_recalc(struct clk *clk) u32 v, plldiv; struct pll_data *pll; - /* Immediate parent must be PLL */ - if (WARN_ON(!clk->parent || !clk->parent->pll_data)) + /* If this is the PLL base clock, no more calculations needed */ + if (clk->pll_data) + return; + + if (WARN_ON(!clk->parent)) return; - pll = clk->parent->pll_data; clk->rate = clk->parent->rate; - /* If bypass divider (BPDIV) use input reference clock */ - if (clk->div_reg == BPDIV) + /* Otherwise, the parent must be a PLL */ + if (WARN_ON(!clk->parent->pll_data)) + return; + + pll = clk->parent->pll_data; + + /* If pre-PLL, source clock is before the multiplier and divider(s) */ + if (clk->flags & PRE_PLL) clk->rate = pll->input_rate; + if (!clk->div_reg) + return; + v = __raw_readl(pll->base + clk->div_reg); if (v & PLLDIV_EN) { plldiv = (v & PLLDIV_RATIO_MASK) + 1; @@ -362,12 +373,13 @@ int __init davinci_clk_init(struct clk *clocks[]) while ((clkp = clocks[i++])) { if (clkp->pll_data) clk_pll_init(clkp); - clk_register(clkp); /* Calculate rates for PLL-derived clocks */ - if (clkp->div_reg) + else if (clkp->flags & CLK_PLL) clk_sysclk_recalc(clkp); + clk_register(clkp); + /* FIXME: remove equivalent special-cased code from * davinci_psc_init() once cpus list *all* clocks. */ diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 428edcf..ecbb71c 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -71,7 +71,8 @@ struct clk { /* Clock flags */ #define ALWAYS_ENABLED BIT(1) -#define CLK_PLL BIT(2) +#define CLK_PLL BIT(2) /* PLL-derived clock */ +#define PRE_PLL BIT(3) /* source is before PLL mult/div */ int davinci_clk_associate(struct device *dev, const char *logical_clockname, const char *physical_clockname); diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 8286753..e5aec41 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -37,7 +37,6 @@ static struct clk ref_clk = { .name = "ref_clk", /* FIXME -- crystal rate is board-specific */ .rate = DM355_REF_FREQ, - .flags = CLK_PLL, }; static struct clk pll1_clk = { @@ -47,80 +46,112 @@ static struct clk pll1_clk = { .pll_data = &pll1_data, }; -static struct clk pll2_clk = { - .name = "pll2", - .parent = &ref_clk, - .flags = CLK_PLL, - .pll_data = &pll2_data, -}; - -static struct clk aux_clk = { - .name = "aux_clk", - .parent = &ref_clk, - .flags = CLK_PLL, +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, }; -static struct clk sysclk1_clk = { - .name = "SYSCLK1", +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV1, }; -static struct clk sysclk2_clk = { - .name = "SYSCLK2", +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV2, }; -static struct clk vpbe_clk = { /* a.k.a. PLL1.SYSCLK3 */ - .name = "vpbe", +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV3, }; -static struct clk vpss_clk = { /* a.k.a. PLL1.SYCLK4 */ - .name = "vpss", +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV4, }; +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk vpbe_clk = { + .name = "vpbe", + .parent = &pll1_sysclk3, +}; + +static struct clk vpss_master_clk = { + .name = "vpss_master", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_VPSSMSTR, +}; + +static struct clk vpss_slave_clk = { + .name = "vpss_slave", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_VPSSSLV, +}; + + static struct clk clkout1_clk = { .name = "clkout1", - .parent = &aux_clk, - .flags = CLK_PLL, + .parent = &pll1_aux_clk, /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */ }; -static struct clk clkout2_clk = { /* a.k.a. PLL1.SYSCLKBP */ +static struct clk clkout2_clk = { .name = "clkout2", - .parent = &pll1_clk, + .parent = &pll1_sysclkbp, +}; + +static struct clk pll2_clk = { + .name = "pll2", + .parent = &ref_clk, + .flags = CLK_PLL, + .pll_data = &pll2_data, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, .flags = CLK_PLL, - .div_reg = BPDIV, + .div_reg = PLLDIV1, +}; + +static struct clk pll2_sysclkbp = { + .name = "pll2_sysclkbp", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV }; static struct clk clkout3_clk = { .name = "clkout3", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = BPDIV, + .parent = &pll2_sysclkbp, /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */ }; static struct clk arm_clk = { .name = "ARMCLK", - .parent = &sysclk1_clk, - .flags = ALWAYS_ENABLED | CLK_PLL, + .parent = &pll1_sysclk1, + .flags = ALWAYS_ENABLED, }; /* * NOT LISTED below, but turned on by PSC init: * - in SyncReset state by default - * .lpsc = DAVINCI_LPSC_VPSSMSTR, .parent = &vpss_clk, - * .lpsc = DAVINCI_LPSC_VPSSSLV, .parent = &vpss_clk, * .lpsc = DAVINCI_LPSC_TPCC, * .lpsc = DAVINCI_LPSC_TPTC0, * .lpsc = DAVINCI_LPSC_TPTC1, @@ -128,7 +159,7 @@ static struct clk arm_clk = { * NOT LISTED below, and not touched by Linux * - in SyncReset state by default * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk, - * .lpsc = DM355_LPSC_RT0, .parent = &aux_clk, + * .lpsc = DM355_LPSC_RT0, .parent = &pll1_aux_clk, * .lpsc = DAVINCI_LPSC_MEMSTICK, * .lpsc = 41, .parent = &vpss_clk, // VPSS DAC * - in Enabled state by default @@ -144,153 +175,158 @@ static struct clk arm_clk = { static struct clk mjcp_clk = { .name = "mjcp", - .parent = &sysclk1_clk, + .parent = &pll1_sysclk1, .lpsc = DAVINCI_LPSC_IMCOP, }; static struct clk uart0_clk = { .name = "uart0", - .parent = &aux_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_UART0, }; static struct clk uart1_clk = { .name = "uart1", - .parent = &aux_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_UART1, }; static struct clk uart2_clk = { .name = "uart2", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_UART2, }; static struct clk i2c_clk = { .name = "I2CCLK", - .parent = &aux_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_I2C, }; static struct clk asp0_clk = { .name = "asp0_clk", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_McBSP, }; static struct clk asp1_clk = { .name = "asp1_clk", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DM355_LPSC_McBSP1, }; static struct clk mmcsd0_clk = { .name = "MMCSDCLK0", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_MMC_SD, }; static struct clk mmcsd1_clk = { .name = "MMCSDCLK1", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DM355_LPSC_MMC_SD1, }; static struct clk spi0_clk = { .name = "SPICLK", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_SPI, }; static struct clk spi1_clk = { .name = "SPICLK1", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DM355_LPSC_SPI1, }; static struct clk spi2_clk = { .name = "SPICLK2", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DM355_LPSC_SPI2, }; static struct clk gpio_clk = { .name = "gpio", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_GPIO, }; static struct clk aemif_clk = { - .name = "AEMIFCLK", - .parent = &sysclk2_clk, + .name = "aemif", + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_AEMIF, - .usecount = 1, }; static struct clk pwm0_clk = { - .name = "PWM0_CLK", - .parent = &aux_clk, + .name = "pwm0", + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_PWM0, }; static struct clk pwm1_clk = { - .name = "PWM1_CLK", - .parent = &aux_clk, + .name = "pwm1", + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_PWM1, }; static struct clk pwm2_clk = { - .name = "PWM2_CLK", - .parent = &aux_clk, + .name = "pwm2", + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_PWM2, }; static struct clk pwm3_clk = { - .name = "PWM3_CLK", - .parent = &aux_clk, + .name = "pwm3", + .parent = &pll1_aux_clk, .lpsc = DM355_LPSC_PWM3, }; static struct clk timer0_clk = { .name = "timer0", - .parent = &aux_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER0, }; static struct clk timer1_clk = { .name = "timer1", - .parent = &aux_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER1, }; static struct clk timer2_clk = { .name = "timer2", - .parent = &aux_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER2, }; static struct clk timer3_clk = { .name = "timer3", - .parent = &aux_clk, + .parent = &pll1_aux_clk, .lpsc = DM355_LPSC_TIMER3, }; static struct clk usb_clk = { .name = "USBCLK", - .parent = &sysclk2_clk, + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_USB, }; static struct clk *dm355_clks[] __initdata = { &ref_clk, &pll1_clk, - &aux_clk, - &sysclk1_clk, - &sysclk2_clk, + &pll1_sysclk1, + &pll1_sysclk2, + &pll1_sysclk3, + &pll1_sysclk4, + &pll1_aux_clk, + &pll1_sysclkbp, &vpbe_clk, - &vpss_clk, + &vpss_master_clk, + &vpss_slave_clk, &clkout1_clk, &clkout2_clk, &pll2_clk, + &pll2_sysclk1, + &pll2_sysclkbp, &clkout3_clk, &arm_clk, &mjcp_clk, diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 680b1dd..308d3cf 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -34,7 +34,6 @@ static struct pll_data pll2_data = { static struct clk ref_clk = { .name = "ref_clk", .rate = DM644X_REF_FREQ, - .flags = CLK_PLL, }; static struct clk pll1_clk = { @@ -44,154 +43,232 @@ static struct clk pll1_clk = { .flags = CLK_PLL, }; -static struct clk pll2_clk = { - .name = "pll2", - .parent = &ref_clk, - .pll_data = &pll2_data, - .flags = CLK_PLL, -}; - -static struct clk sysclk1_clk = { - .name = "SYSCLK1", +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV1, }; -static struct clk sysclk2_clk = { - .name = "SYSCLK2", +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV2, }; -static struct clk sysclk3_clk = { - .name = "SYSCLK3", +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV3, }; -static struct clk sysclk5_clk = { - .name = "SYSCLK5", +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV5, }; +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk pll2_clk = { + .name = "pll2", + .parent = &ref_clk, + .pll_data = &pll2_data, + .flags = CLK_PLL, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll2_sysclk2 = { + .name = "pll2_sysclk2", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll2_sysclkbp = { + .name = "pll2_sysclkbp", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + static struct clk arm_clk = { - .name = "ARMCLK", - .parent = &sysclk2_clk, + .name = "arm", + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_NONE, .flags = ALWAYS_ENABLED, }; +static struct clk vicp_clk = { + .name = "vicp", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_IMCOP, +}; + +static struct clk vpss_master_clk = { + .name = "vpss_master", + .parent = &pll1_sysclk3, + .lpsc = DAVINCI_LPSC_VPSSMSTR, +}; + +static struct clk vpss_slave_clk = { + .name = "vpss_slave", + .parent = &pll1_sysclk3, + .lpsc = DAVINCI_LPSC_VPSSSLV, +}; + static struct clk uart0_clk = { .name = "uart0", - .parent = &ref_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_UART0, }; static struct clk uart1_clk = { .name = "uart1", - .parent = &ref_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_UART1, }; static struct clk uart2_clk = { .name = "uart2", - .parent = &ref_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_UART2, }; static struct clk emac_clk = { .name = "EMACCLK", - .parent = &sysclk5_clk, + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, }; static struct clk i2c_clk = { .name = "I2CCLK", - .parent = &ref_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_I2C, }; static struct clk ide_clk = { .name = "IDECLK", - .parent = &sysclk5_clk, + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_ATA, }; static struct clk asp_clk = { .name = "asp0_clk", - .parent = &sysclk5_clk, + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_McBSP, }; static struct clk mmcsd_clk = { .name = "MMCSDCLK", - .parent = &sysclk5_clk, + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_MMC_SD, }; static struct clk spi_clk = { - .name = "SPICLK", - .parent = &sysclk5_clk, + .name = "spi", + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_SPI, }; static struct clk gpio_clk = { .name = "gpio", - .parent = &sysclk5_clk, + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_GPIO, }; static struct clk usb_clk = { .name = "USBCLK", - .parent = &sysclk5_clk, + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_USB, }; static struct clk vlynq_clk = { .name = "VLYNQCLK", - .parent = &sysclk5_clk, + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_VLYNQ, }; static struct clk aemif_clk = { - .name = "AEMIFCLK", - .parent = &sysclk5_clk, + .name = "aemif", + .parent = &pll1_sysclk5, .lpsc = DAVINCI_LPSC_AEMIF, .flags = ALWAYS_ENABLED, }; +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM0, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM1, +}; + +static struct clk pwm2_clk = { + .name = "pwm2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM2, +}; + static struct clk timer0_clk = { .name = "timer0", - .parent = &ref_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER0, }; static struct clk timer1_clk = { .name = "timer1", - .parent = &ref_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER1, }; static struct clk timer2_clk = { .name = "timer2", - .parent = &ref_clk, + .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER2, }; static struct clk *dm644x_clks[] __initdata = { &ref_clk, &pll1_clk, + &pll1_sysclk1, + &pll1_sysclk2, + &pll1_sysclk3, + &pll1_sysclk5, + &pll1_aux_clk, + &pll1_sysclkbp, &pll2_clk, - &sysclk1_clk, - &sysclk2_clk, - &sysclk3_clk, - &sysclk5_clk, + &pll2_sysclk1, + &pll2_sysclk2, + &pll2_sysclkbp, &arm_clk, + &vicp_clk, + &vpss_master_clk, + &vpss_slave_clk, &uart0_clk, &uart1_clk, &uart2_clk, @@ -205,6 +282,9 @@ static struct clk *dm644x_clks[] __initdata = { &usb_clk, &vlynq_clk, &aemif_clk, + &pwm0_clk, + &pwm1_clk, + &pwm2_clk, &timer0_clk, &timer1_clk, &timer2_clk, diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 3f54872..94bde32 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -36,13 +36,11 @@ static struct pll_data pll2_data = { static struct clk ref_clk = { .name = "ref_clk", .rate = DM646X_REF_FREQ, - .flags = CLK_PLL, }; -static struct clk aux_clk = { - .name = "aux_clk", +static struct clk aux_clkin = { + .name = "aux_clkin", .rate = DM646X_AUX_FREQ, - .flags = CLK_PLL, }; static struct clk pll1_clk = { @@ -52,151 +50,179 @@ static struct clk pll1_clk = { .flags = CLK_PLL, }; -static struct clk pll2_clk = { - .name = "pll2", - .parent = &ref_clk, - .pll_data = &pll2_data, - .flags = CLK_PLL, -}; - -static struct clk sysclk1_clk = { - .name = "SYSCLK1", +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV1, }; -static struct clk sysclk2_clk = { - .name = "SYSCLK2", +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV2, }; -static struct clk sysclk3_clk = { - .name = "SYSCLK3", +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV3, }; -static struct clk sysclk4_clk = { - .name = "SYSCLK4", +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV4, }; -static struct clk sysclk5_clk = { - .name = "SYSCLK5", +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV5, }; -static struct clk sysclk6_clk = { - .name = "SYSCLK6", +static struct clk pll1_sysclk6 = { + .name = "pll1_sysclk6", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV6, }; -static struct clk sysclk8_clk = { - .name = "SYSCLK8", +static struct clk pll1_sysclk8 = { + .name = "pll1_sysclk8", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV8, }; -static struct clk sysclk9_clk = { - .name = "SYSCLK9", +static struct clk pll1_sysclk9 = { + .name = "pll1_sysclk9", .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV9, }; -static struct clk sysclkbp_clk = { - .name = "SYSCLKBP", +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", .parent = &pll1_clk, - .flags = CLK_PLL, + .flags = CLK_PLL | PRE_PLL, .div_reg = BPDIV, }; +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll2_clk = { + .name = "pll2_clk", + .parent = &ref_clk, + .pll_data = &pll2_data, + .flags = CLK_PLL, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + static struct clk arm_clk = { - .name = "ARMCLK", - .parent = &sysclk2_clk, + .name = "arm", + .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_NONE, .flags = ALWAYS_ENABLED, }; static struct clk uart0_clk = { .name = "uart0", - .parent = &aux_clk, + .parent = &aux_clkin, .lpsc = DM646X_LPSC_UART0, }; static struct clk uart1_clk = { .name = "uart1", - .parent = &aux_clk, + .parent = &aux_clkin, .lpsc = DM646X_LPSC_UART1, }; static struct clk uart2_clk = { .name = "uart2", - .parent = &aux_clk, + .parent = &aux_clkin, .lpsc = DM646X_LPSC_UART2, }; static struct clk i2c_clk = { .name = "I2CCLK", - .parent = &sysclk3_clk, + .parent = &pll1_sysclk3, .lpsc = DM646X_LPSC_I2C, }; static struct clk gpio_clk = { .name = "gpio", - .parent = &sysclk3_clk, + .parent = &pll1_sysclk3, .lpsc = DM646X_LPSC_GPIO, }; static struct clk aemif_clk = { - .name = "AEMIFCLK", - .parent = &sysclk3_clk, + .name = "aemif", + .parent = &pll1_sysclk3, .lpsc = DM646X_LPSC_AEMIF, .flags = ALWAYS_ENABLED, }; static struct clk emac_clk = { .name = "EMACCLK", - .parent = &sysclk3_clk, + .parent = &pll1_sysclk3, .lpsc = DM646X_LPSC_EMAC, }; +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_PWM0, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_PWM1, +}; + static struct clk timer0_clk = { .name = "timer0", - .parent = &sysclk3_clk, + .parent = &pll1_sysclk3, .lpsc = DM646X_LPSC_TIMER0, }; static struct clk timer1_clk = { .name = "timer1", - .parent = &sysclk3_clk, + .parent = &pll1_sysclk3, .lpsc = DM646X_LPSC_TIMER1, }; static struct clk *dm646x_clks[] __initdata = { &ref_clk, + &aux_clkin, &pll1_clk, - &sysclk1_clk, - &sysclk2_clk, - &sysclk3_clk, - &sysclk4_clk, - &sysclk5_clk, - &sysclk6_clk, - &sysclk8_clk, - &sysclk9_clk, - &sysclkbp_clk, + &pll1_sysclk1, + &pll1_sysclk2, + &pll1_sysclk3, + &pll1_sysclk4, + &pll1_sysclk5, + &pll1_sysclk6, + &pll1_sysclk8, + &pll1_sysclk9, + &pll1_sysclkbp, + &pll1_aux_clk, &pll2_clk, + &pll2_sysclk1, &arm_clk, &uart0_clk, &uart1_clk, @@ -205,6 +231,8 @@ static struct clk *dm646x_clks[] __initdata = { &gpio_clk, &aemif_clk, &emac_clk, + &pwm0_clk, + &pwm1_clk, &timer0_clk, &timer1_clk, NULL, diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 1859a53..6117529 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -190,10 +190,6 @@ void __init davinci_psc_init(void) if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm355()) { davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, - DAVINCI_LPSC_VPSSMSTR, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, - DAVINCI_LPSC_VPSSSLV, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1); davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1); diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index f279013..cf56de1 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -438,16 +438,17 @@ static int __init nand_davinci_probe(struct platform_device *pdev) } info->chip.ecc.mode = ecc_mode; - info->clk = clk_get(&pdev->dev, "AEMIFCLK"); + info->clk = clk_get(&pdev->dev, "aemif"); if (IS_ERR(info->clk)) { ret = PTR_ERR(info->clk); - dev_dbg(&pdev->dev, "unable to get AEMIFCLK, err %d\n", ret); + dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); goto err_clk; } ret = clk_enable(info->clk); if (ret < 0) { - dev_dbg(&pdev->dev, "unable to enable AEMIFCLK, err %d\n", ret); + dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", + ret); goto err_clk_enable; } -- 1.6.1 _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
