More followon updates ... clock trees are more complete,
also notice the new PSC_DSP flag (only on dm644x for now).
However, that flag doesn't quite seem sufficient to disable
the DSP and VICP clocks on my ancient dm6446 chip.
- Dave
====================
More small clock tweaks:
- Add PSC_DSP flag for updating dm644x DSP and VICP clocks
- When disabling unused clocks, avoid WARN() spewage
- Flag oscillators with LPSC_NONE; in procfs, don't label non-PSC clocks
- Use the right LPSC entries for the ARM cores
- On dm355, list two more clocks
- On dm64xx, list the DSP clocks too
- Correct some LPSC definitions: remove invalid, define dm646x ARM
- AEMIF shouldn't be "always enabled" on dm6446 (EVM may need NOR tweaks)
So most non-EDMA clocks are covered now, at least on dm335 and dm6446.
Exception include HPI and the other EMAC clock on dm644x.
Note that CONFIG_DAVINCI_RESET_CLOCKS was wedging when disabling the
two DSP domain clocks on dm6446, so there's a workaround in place to
prevent that.
---
arch/arm/mach-davinci/clock.c | 27 ++++++++++++++++++++-------
arch/arm/mach-davinci/clock.h | 1 +
arch/arm/mach-davinci/dm355.c | 18 ++++++++++++++++--
arch/arm/mach-davinci/dm644x.c | 15 +++++++++++++--
arch/arm/mach-davinci/dm646x.c | 11 ++++++++++-
arch/arm/mach-davinci/include/mach/psc.h | 6 ++----
6 files changed, 62 insertions(+), 16 deletions(-)
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -138,12 +138,19 @@ void clk_put(struct clk *clk)
}
EXPORT_SYMBOL(clk_put);
+static unsigned psc_domain(struct clk *clk)
+{
+ return (clk->flags & PSC_DSP)
+ ? DAVINCI_GPSC_DSPDOMAIN
+ : DAVINCI_GPSC_ARMDOMAIN;
+}
+
static void __clk_enable(struct clk *clk)
{
if (clk->parent)
__clk_enable(clk->parent);
if (clk->usecount++ == 0 && !(clk->flags & CLK_PLL))
- davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
+ davinci_psc_config(psc_domain(clk), clk->lpsc, 1);
}
static void __clk_disable(struct clk *clk)
@@ -151,7 +158,7 @@ static void __clk_disable(struct clk *cl
if (WARN_ON(clk->usecount == 0))
return;
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
- davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0);
+ davinci_psc_config(psc_domain(clk), clk->lpsc, 0);
if (clk->parent)
__clk_disable(clk->parent);
}
@@ -256,17 +263,20 @@ EXPORT_SYMBOL(clk_unregister);
static int __init clk_disable_unused(void)
{
struct clk *ck;
- unsigned long flags;
+ spin_lock_irq(&clockfw_lock);
list_for_each_entry(ck, &clocks, node) {
if (ck->usecount > 0)
continue;
+ if (ck->flags & CLK_PLL)
+ continue;
+ if (ck->lpsc == DAVINCI_LPSC_NONE)
+ continue;
printk(KERN_INFO "Clocks: disable unused %s\n", ck->name);
- spin_lock_irqsave(&clockfw_lock, flags);
- __clk_disable(ck);
- spin_unlock_irqrestore(&clockfw_lock, flags);
+ davinci_psc_config(psc_domain(ck), ck->lpsc, 0);
}
+ spin_unlock_irq(&clockfw_lock);
return 0;
}
@@ -423,7 +433,10 @@ dump_clock(struct seq_file *s, unsigned
struct clk *clk;
unsigned i;
- state = (parent->flags & CLK_PLL) ? "pll" : "psc";
+ if (!(parent->flags & CLK_PLL) && parent->lpsc != DAVINCI_LPSC_NONE)
+ state = "psc";
+ else
+ state = "";
/* <nest spaces> name <pad to end> */
memset(buf, ' ', sizeof(buf) - 1);
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -73,6 +73,7 @@ struct clk {
#define ALWAYS_ENABLED BIT(1)
#define CLK_PLL BIT(2) /* PLL-derived clock */
#define PRE_PLL BIT(3) /* source is before PLL mult/div */
+#define PSC_DSP BIT(4) /* PSC uses DSP domain, not ARM */
int davinci_clk_associate(struct device *dev, const char *logical_clockname,
const char *physical_clockname);
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -41,6 +41,7 @@ static struct clk ref_clk = {
.name = "ref_clk",
/* FIXME -- crystal rate is board-specific */
.rate = DM355_REF_FREQ,
+ .lpsc = DAVINCI_LPSC_NONE,
};
static struct clk pll1_clk = {
@@ -96,6 +97,12 @@ static struct clk vpbe_clk = {
.parent = &pll1_sysclk3,
};
+static struct clk vpss_dac_clk = {
+ .name = "vpss_dac",
+ .parent = &pll1_sysclk3,
+ .lpsc = DM355_LPSC_VPSS_DAC,
+};
+
static struct clk vpss_master_clk = {
.name = "vpss_master",
.parent = &pll1_sysclk4,
@@ -150,6 +157,7 @@ static struct clk clkout3_clk = {
static struct clk arm_clk = {
.name = "ARMCLK",
.parent = &pll1_sysclk1,
+ .lpsc = DAVINCI_LPSC_ARM,
.flags = ALWAYS_ENABLED,
};
@@ -163,9 +171,7 @@ static struct clk arm_clk = {
* NOT LISTED below, and not touched by Linux
* - in SyncReset state by default
* .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
- * .lpsc = DM355_LPSC_RT0, .parent = &pll1_aux_clk,
* .lpsc = DAVINCI_LPSC_MEMSTICK,
- * .lpsc = 41, .parent = &vpss_clk, // VPSS DAC
* - in Enabled state by default
* .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
* .lpsc = DAVINCI_LPSC_SCR2, // "bus"
@@ -308,6 +314,12 @@ static struct clk timer3_clk = {
.lpsc = DM355_LPSC_TIMER3,
};
+static struct clk rto_clk = {
+ .name = "rto",
+ .parent = &pll1_aux_clk,
+ .lpsc = DM355_LPSC_RTO,
+};
+
static struct clk usb_clk = {
.name = "USBCLK",
.parent = &pll1_sysclk2,
@@ -324,6 +336,7 @@ static struct clk *dm355_clks[] __initda
&pll1_aux_clk,
&pll1_sysclkbp,
&vpbe_clk,
+ &vpss_dac_clk,
&vpss_master_clk,
&vpss_slave_clk,
&clkout1_clk,
@@ -355,6 +368,7 @@ static struct clk *dm355_clks[] __initda
&timer1_clk,
&timer2_clk,
&timer3_clk,
+ &rto_clk,
&usb_clk,
NULL,
};
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -34,6 +34,7 @@ static struct pll_data pll2_data = {
static struct clk ref_clk = {
.name = "ref_clk",
.rate = DM644X_REF_FREQ,
+ .lpsc = DAVINCI_LPSC_NONE,
};
static struct clk pll1_clk = {
@@ -112,10 +113,18 @@ static struct clk pll2_sysclkbp = {
.div_reg = BPDIV
};
+static struct clk dsp_clk = {
+ .name = "dsp",
+ .parent = &pll1_sysclk1,
+ .lpsc = DAVINCI_LPSC_GEM,
+ .flags = PSC_DSP,
+ .usecount = 1, /* REVISIT how to disable? */
+};
+
static struct clk arm_clk = {
.name = "arm",
.parent = &pll1_sysclk2,
- .lpsc = DAVINCI_LPSC_NONE,
+ .lpsc = DAVINCI_LPSC_ARM,
.flags = ALWAYS_ENABLED,
};
@@ -123,6 +132,8 @@ static struct clk vicp_clk = {
.name = "vicp",
.parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_IMCOP,
+ .flags = PSC_DSP,
+ .usecount = 1, /* REVISIT how to disable? */
};
static struct clk vpss_master_clk = {
@@ -213,7 +224,6 @@ static struct clk aemif_clk = {
.name = "aemif",
.parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_AEMIF,
- .flags = ALWAYS_ENABLED,
};
static struct clk pwm0_clk = {
@@ -265,6 +275,7 @@ static struct clk *dm644x_clks[] __initd
&pll2_sysclk1,
&pll2_sysclk2,
&pll2_sysclkbp,
+ &dsp_clk,
&arm_clk,
&vicp_clk,
&vpss_master_clk,
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -36,11 +36,13 @@ static struct pll_data pll2_data = {
static struct clk ref_clk = {
.name = "ref_clk",
.rate = DM646X_REF_FREQ,
+ .lpsc = DAVINCI_LPSC_NONE,
};
static struct clk aux_clkin = {
.name = "aux_clkin",
.rate = DM646X_AUX_FREQ,
+ .lpsc = DAVINCI_LPSC_NONE,
};
static struct clk pll1_clk = {
@@ -133,10 +135,16 @@ static struct clk pll2_sysclk1 = {
.div_reg = PLLDIV1,
};
+static struct clk dsp_clk = {
+ .name = "dsp",
+ .parent = &pll1_sysclk1,
+ .lpsc = DM646X_LPSC_C64X_CPU,
+};
+
static struct clk arm_clk = {
.name = "arm",
.parent = &pll1_sysclk2,
- .lpsc = DAVINCI_LPSC_NONE,
+ .lpsc = DM646X_LPSC_ARM,
.flags = ALWAYS_ENABLED,
};
@@ -223,6 +231,7 @@ static struct clk *dm646x_clks[] __initd
&pll1_aux_clk,
&pll2_clk,
&pll2_sysclk1,
+ &dsp_clk,
&arm_clk,
&uart0_clk,
&uart1_clk,
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -40,8 +40,6 @@
#define DAVINCI_LPSC_TPTC1 4
#define DAVINCI_LPSC_EMAC 5
#define DAVINCI_LPSC_EMAC_WRAPPER 6
-#define DAVINCI_LPSC_MDIO 7
-#define DAVINCI_LPSC_IEEE1394 8
#define DAVINCI_LPSC_USB 9
#define DAVINCI_LPSC_ATA 10
#define DAVINCI_LPSC_VLYNQ 11
@@ -49,7 +47,6 @@
#define DAVINCI_LPSC_DDR_EMIF 13
#define DAVINCI_LPSC_AEMIF 14
#define DAVINCI_LPSC_MMC_SD 15
-#define DAVINCI_LPSC_MEMSTICK 16
#define DAVINCI_LPSC_McBSP 17
#define DAVINCI_LPSC_I2C 18
#define DAVINCI_LPSC_UART0 19
@@ -82,11 +79,12 @@
#define DM355_LPSC_PWM3 10
#define DM355_LPSC_SPI2 11
#define DM355_LPSC_RTO 12
+#define DM355_LPSC_VPSS_DAC 41
/*
* LPSC Assignments
*/
-#define DM646X_LPSC_RESERVED 0
+#define DM646X_LPSC_ARM 0
#define DM646X_LPSC_C64X_CPU 1
#define DM646X_LPSC_HDVICP0 2
#define DM646X_LPSC_HDVICP1 3
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