Here are the last few instructions prior to the failure on the failing
version, thanks to the CP TRACE facility under z/VM on a real IBM z/890:
0000000000002A78 STG E310F0A80024 >> 000000000000FEB0 CC 2
0000000000002A7E LG E32030000004 00000000000001B0 CC 2
0000000000002A84 LG E31030080004 00000000000001B8 CC 2
0000000000002A8A STG E34030000024 >> 00000000000001B0 CC 2
0000000000002A90 LA 4140F0A0 = 000000000000FEA8 CC 2
0000000000002A94 LARL C0500000000B CC 2
0000000000002A9A STG E35040080024 >> 000000000000FEB0 CC 2
0000000000002AA0 STG E35030080024 >> 00000000000001B8 CC 2
0000000000002AA6 LPSWE B2B2F0A0 000000000000FEA8 CC 0
0000000000002AAA LMG EBDFF0B00004 ???????????????? CC 0
0000000000002AB0 STG E32030000024 >> 00000000000001B0 CC 0
0000000000002AB6 STG E31030080024 >> 00000000000001B8 CC 0
0000000000002ABC BR 07FE -> 00000000000032E6 CC 0
-> 00000000000032E6 LH 48100086 0000000000000086 CC 0
00000000000032EA BRU A7F40001 -> 00000000000032EC CC 0
-> 00000000000032EC ???? 0001
*** 00000000000032EC PROG 0001 -> 00000000000039A8
And here is what appears to be the equivalent code on the working
version, compiled under wheezy:
0000000000002A38 STG E310F0A80024 >> 000000000000FEA0 CC 2
0000000000002A3E LG E32030000004 00000000000001B0 CC 2
0000000000002A44 LG E31030080004 00000000000001B8 CC 2
0000000000002A4A STG E34030000024 >> 00000000000001B0 CC 2
0000000000002A50 LA 4140F0A0 = 000000000000FE98 CC 2
0000000000002A54 LARL C0500000000B CC 2
0000000000002A5A STG E35040080024 >> 000000000000FEA0 CC 2
0000000000002A60 STG E35030080024 >> 00000000000001B8 CC 2
0000000000002A66 LPSWE B2B2F0A0 000000000000FE98 CC 0
0000000000002A6A LMG EBDFF0B00004 ???????????????? CC 0
0000000000002A70 STG E32030000024 >> 00000000000001B0 CC 0
0000000000002A76 STG E31030080024 >> 00000000000001B8 CC 0
0000000000002A7C BR 07FE -> 00000000000032C0 CC 0
-> 00000000000032C0 LLGH E31000860091 0000000000000086 CC 0
00000000000032C6 CHI A71E1004 CC 2
00000000000032CA BRZ A784000A 00000000000032DE CC 2
...
And on we go from there. The BRU instruction in the first sequence
is clearly bad. In assembler language format, the equivalent instruction
would be "BRU *+2". This is a bad branch. The instruction branches
into the middle of itself, picking up "0001" as the next machine instruction,
which causes an operation exception. Since the failing "instruction"
starts at storage address 32EC, and is two bytes long, that means that
the updated instruction address in the PSW at the time of the program
interruption will be 32EE, which is the value used in the disabled wait
PSW.
--
.''`. Stephen Powell
: :' :
`. `'`
`-
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