Thorsten Behrens wrote:
Jens-Heiner Rechtien <[EMAIL PROTECTED]> writes:
BTW, on newer processors (P4, Xeon etc) the "lock" prefix shouldn't be
that expensive, because if the target memory of the instruction is
cacheable the CPU will not assert the Lock# signal (which locks the
bus) but only lock the affected cache line.
Wasn't Stephan's original measurement based on a P4 ("model name:
Intel(R) Pentium(R) 4 CPU 1.80GHz"), with a factor-eight slowdown?
I think that Intel changed the behavior with the introduction of HT in
Pentium 4, so Stefans machine is still one which locks the whole bus.
Could be wrong here, though.
So, how to go forward from here? Is anybody trying out/profiling the
proposed changes (switch on multi-coreness, inlining)?
I volunteer for that, but I got two projects to finish before that, so
it could take a little time.
Heiner
--
Jens-Heiner Rechtien
[EMAIL PROTECTED]
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