The logic in the init routine for the TSI148 is inverted. It isn't switching
on the CR/CSR space when it should be and is reporting it's on when its not.
Correct the logic to do the right thing.
Reported-by: De Roo, Steven <steven.de...@arcelormittal.com>
Signed-off-by: Martyn Welch <martyn.we...@ge.com>
---
drivers/vme/bridges/vme_tsi148.c | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/vme/bridges/vme_tsi148.c b/drivers/vme/bridges/vme_tsi148.c
index 94ce64d..c04600e 100644
--- a/drivers/vme/bridges/vme_tsi148.c
+++ b/drivers/vme/bridges/vme_tsi148.c
@@ -2300,12 +2300,13 @@ static int tsi148_crcsr_init(struct vme_bridge
*tsi148_bridge,
dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
- if (crat & TSI148_LCSR_CRAT_EN) {
+ if (crat & TSI148_LCSR_CRAT_EN)
+ dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
+ else {
dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
iowrite32be(crat | TSI148_LCSR_CRAT_EN,
bridge->base + TSI148_LCSR_CRAT);
- } else
- dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
+ }
/* If we want flushed, error-checked writes, set up a window
* over the CR/CSR registers. We read from here to safely flush
--
1.7.0.4
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