Hi, On 04/23/2015 03:39 PM, Florent Kermarrec wrote: > For 1) I just added names to what is done (reg_initialization, > blocking_assign, dummy signal) and what is done for ASIC is now > clearly understandable just looking at ASICSyntaxSettings. > For 2) I'm just want to expose the syntax specialization parameters to > the user to allow the user to use these. > > The main reason I'd like to have 2) is to provide clean code to my > customers and avoid having to justify myself about what is this dummy > signal and what is is intended for...
That may be a good reason, but you also have to consider that without the dummy signal, the generated code may not simulate correctly anymore in event-driven simulators. Also note that initialization of signals generated in combinatorial "always" blocks is a general problem with Verilog programming, even in manually written code. Perhaps renaming the "dummy" signal to e.g. "initialize_always_comb" would help, along with a note in the Migen documentation explaining what it does? Sébastien _______________________________________________ M-Labs devel mailing list https://ssl.serverraum.org/lists/listinfo/devel
