Some comments from the ASIC world: - initial statements and variable initializers are not synthesizable by either Design Compiler or RTL Compiler, both treat these as a syntax error. Both tools are very similar in what they consider to be the synthesizable subset.
- Nonblocking assigns I believe are just a warning but required by company coding guidelines (at least all companies I have worked for). All lint tools (and fellow ASIC designers) I'm familiar with will flag this. - Not sure where the dummy signal comes from, but I suspect its an order of events problem related to use of initial blocks. Not needed for blocks with an explicit reset. Also not guaranteed to work across simulators, since they are free to order events in any way they choose. - Guy On Thu, Apr 23, 2015 at 12:46 AM, Sébastien Bourdeauducq <[email protected]> wrote: > Hi, > > On 04/23/2015 03:39 PM, Florent Kermarrec wrote: > > For 1) I just added names to what is done (reg_initialization, > > blocking_assign, dummy signal) and what is done for ASIC is now > > clearly understandable just looking at ASICSyntaxSettings. > > For 2) I'm just want to expose the syntax specialization parameters to > > the user to allow the user to use these. > > > > The main reason I'd like to have 2) is to provide clean code to my > > customers and avoid having to justify myself about what is this dummy > > signal and what is is intended for... > > That may be a good reason, but you also have to consider that without > the dummy signal, the generated code may not simulate correctly anymore > in event-driven simulators. Also note that initialization of signals > generated in combinatorial "always" blocks is a general problem with > Verilog programming, even in manually written code. > > Perhaps renaming the "dummy" signal to e.g. "initialize_always_comb" > would help, along with a note in the Migen documentation explaining what > it does? > > Sébastien > > _______________________________________________ > M-Labs devel mailing list > https://ssl.serverraum.org/lists/listinfo/devel >
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