Hi, On Tuesday 20 October 2009 11:45:19 you wrote: > Sébastien> I am planning to use 6 layers, with 6 mil width and spacing, > Sébastien> without special features. This is however only a plan, I may > Sébastien> change those rules if routing turns out to be too difficult. > > With two supply layers you have 4 routing layers. Roughly you can fan out 2 > rows of balls on top and another row with each layer, as each via takes 600 > um with 300 um standard drill and leave only space to pass one signal with > space/line/space 450 um. So I guess you can bring out not so many of the > available Pins, if my estimation has no fundamental flaw.
You are probably right. I did not have time to look for the BGA routing yet - I have been busy with choosing parts and the schematics. However, the number of required FPGA I/O is small (199/316) and I have already routed a board with a BGA320 and these constraints. There were unconnected pins of course, and I was using FPGA pin-swapping to solve some problems. It might be harder here, mostly because I want to use DDR SDRAM memory with a pinout compatible with the Spartan-6 MCB (in case I choose to use it later on) and at high frequencies (400Mbps/pin) which mean short and length-matched tracks. What would you suggest? Best regards, Sébastien _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkym...@freenode Webchat: www.milkymist.org/irc.html Wiki: www.milkymist.org/wiki
