>>>>> "Sébastien" == Sébastien Bourdeauducq
>>>>> <[email protected]> writes:
Sébastien> Hi, On Tuesday 20 October 2009 11:45:19 you wrote: I am
Sébastien> planning to use 6 layers, with 6 mil width and spacing,
Sébastien> without special features. This is however only a plan, I may
Sébastien> change those rules if routing turns out to be too difficult.
>> With two supply layers you have 4 routing layers. Roughly you can
>> fan out 2 rows of balls on top and another row with each layer, as
>> each via takes 600 um with 300 um standard drill and leave only space
>> to pass one signal with space/line/space 450 um. So I guess you can
>> bring out not so many of the available Pins, if my estimation has no
>> fundamental flaw.
Sébastien> You are probably right. I did not have time to look for the
Sébastien> BGA routing yet - I have been busy with choosing parts and
Sébastien> the schematics. However, the number of required FPGA I/O is
Sébastien> small (199/316) and I have already routed a board with a
Sébastien> BGA320 and these constraints. There were unconnected pins of
Sébastien> course, and I was using FPGA pin-swapping to solve some
Sébastien> problems. It might be harder here, mostly because I want to
Sébastien> use DDR SDRAM memory with a pinout compatible with the
Sébastien> Spartan-6 MCB (in case I choose to use it later on) and at
Sébastien> high frequencies (400Mbps/pin) which mean short and
Sébastien> length-matched tracks. What would you suggest?
With the estimation I gave ( reach 2 row on top an one row on each routing
layer) on the 23x23 FGG package you can reach 8*23 and 8*(23-8) = 304
pins. Even with many restrictions for the high speed routing of the
MCB/SDRAM connection, that should work. Do you consider to use the raw MCB
or MIG. If you use MIG, how to you plan to connect to the CPU. Via wishbone
or direct?
Bye
--
Uwe Bonnes [email protected]
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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