On 13/04/11 01:21, Sebastien Bourdeauducq wrote:
On Wed, 2011-04-13 at 00:23 +0100, Philip Pemberton wrote:
- Memory access rights enforcement is left up to an external MMU.
This is going to be slow (and slow is bad).
Why would it be slow?
The MMU checks the logical address against the page tables, then causes
a bus-abort (raise WB_ERR) if the access was disallowed (e.g. user-level
code trying to muck about with the page tables, kernel RAM or hardware
regs).
If the MMU is simple enough (read: AT&T 3B1 style simple) then you could
easily do single-cycle remapping and privilege checking. Latency would
be zero, or very close to it.
Now if you wanted something more like the x86 mapper... that will slow
things down. I spent over a month trying to understand that thing...
never again! Intel can take their hack-on-a-bodge-on-a-kludge
architecture with them to the Special Hell...
> Instead run the TLB lookup
> at the same time as the cache lookup (i.e. virtually indexed and
> physically tagged caches). Yes, this requires messing a bit with the
> CPU pipeline, but let's leave the 30-second-memcpy-of-a-8MB-buffer
> kind of designs to the OpenRISC and ZPU people.
So what you're talking about is slotting the mapper in between the CPU
and cache, mapping the logical address into a physical one before the
cache sees it?
I wonder what effect this would have on the pipeline... a multicycle MMU
probably wouldn't be possible without causing major problems with the
CPU timing.
--
Phil.
[email protected]
http://www.philpem.me.uk/
_______________________________________________
http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org
IRC: #milkymist@Freenode
Twitter: www.twitter.com/milkymistvj
Ideas? http://milkymist.uservoice.com
