On Thu, 2011-04-14 at 21:38 +0200, Lars-Peter Clausen wrote: > If I understand it correctly this looks at lot like ARM Fast Context > Switching: > http://lwn.net/images/conf/rtlws11/papers/proc/p01.pdf
I'd still prefer a VIPT cache with cache associativity * page size = cache size :) Simpler and no restriction on process count or process address space (btw, for my purposes I may need to allocate more than 32MB in a single process). Even the high performance OMAP3503 chip has only a 16K L1 cache, which could be done using this solution with 8K pages and a 2-way associative cache... so it doesn't scale too bad. S. _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode Twitter: www.twitter.com/milkymistvj Ideas? http://milkymist.uservoice.com
