Sebastien Bourdeauducq wrote:
There's always the possibility of throwing a second serial port into
the
FPGA design and connecting it to the GPIO expansion header J21 :)
Hopefully this could even be made to work with the JTAG/serial pod
without too much "mechanical" fuss...
If that's what it takes, let me know the pinout and I can design and
etch a PCB with a pin header plug on one side and a serial port on the
other fairly easily :)
I've got access to everything I need for doing that. That is, if you
think it's really a required step to push this issue forward towards a
solution.
--
hadez
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