On 11/20/2011 10:59 AM, [email protected] wrote:
Hi,
On Sun, 20 Nov 2011 06:07:44 -0300, Werner Almesberger wrote:
So it does indeed seem that the sample clock is running a bit
fast for some reason.
Try sampling 1/4 bit time later?
Didn't work. Also tried deglitching (patch attached) without any visible
improvement.
diff --git a/cores/softusb/rtl/softusb_filter.v
b/cores/softusb/rtl/softusb_filter.v
index 7418d07..2a5d4dd 100644
--- a/cores/softusb/rtl/softusb_filter.v
+++ b/cores/softusb/rtl/softusb_filter.v
@@ -31,14 +31,35 @@ reg rcv_s0;
reg vp_s0;
reg vm_s0;
+reg rcv_s1;
+reg vp_s1;
+reg vm_s1;
+
/* synchronizer */
always @(posedge usb_clk) begin
rcv_s0 <= rcv;
vp_s0 <= vp;
vm_s0 <= vm;
- rcv_s <= rcv_s0;
- vp_s <= vp_s0;
- vm_s <= vm_s0;
+ rcv_s1 <= rcv_s0;
+ vp_s1 <= vp_s0;
+ vm_s1 <= vm_s0;
+end
+
+reg rcv_s2;
+reg vp_s2;
+reg vm_s2;
+
+/* deglitcher */
+always @(posedge usb_clk) begin
+ rcv_s2 <= rcv_s1;
+ vp_s2 <= vp_s1;
+ vm_s2 <= vm_s1;
+ if(rcv_s1 == rcv_s2)
+ rcv_s <= rcv_s2;
+ if(vp_s1 == vp_s2)
+ vp_s <= vp_s2;
+ if(vm_s1 == vm_s2)
+ vm_s <= vm_s2;
end
endmodule
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