Heelo Sebastian.

> 1) This system doesn't seem tied to Wishbone and I think it can be used 
> with most on-chip buses, so perhaps the name should be changed.

Yes, this we realized a few days ago. We were also thinking about
offering smaller versions of the description, i.e. a 16-bit and 32-bit
version, straight from the start (the 16-bit base address will have
a shift applied, so it's not limited to 64kB overall size -- if
all base addresses are 1k-aligned you can span 64MB.

> FYI, Gaisler Research has designed a similar system for AMBA, but I
> do not know how it compares and if it can have some compatibility.

Thanks for the information. I'll let manohar study this and report.

> 2) On-chip memory is an expensive resource, so it would make sense
> to put more accent on code density rather than human readability.

Yes, but still, diagnostic is much easier if you can make sense
of the numbers.  In the current plans most fields are optional
and if you are really short on space the smalle versions can be used
(see above).

> 3) It is more expensive to have several small ROMs than one big ROM. 
> This is particularly true for FPGA implementations where large ROMs can 
> be much more efficiently mapped to block RAM resources (actually, when 
> block RAMs are used, point #2 becomes less valid, since the granularity 
> of those memories is e.g. 1 kilobyte for Spartan-6).

It's not mandatory to have the information spread around, it's only
an option that we don't want to prevent in the specs.

> 4) Point #3 brings me to another reason why Migen should be used :-) 
> When writing Verilog/VHDL directly, you only have the options of having 
> a small ROM in each core (which is wasteful) or writing the main ROM 
> manually (which is not very productive and can lead to errors). By 
> contrast, it would be straightforward and elegant to have the Python 
> objects for cores and bus interconnect register with one central object 
> that builds the ROM.

I can't find "migen" I'm sorry. Can you expand on this?
(I agree with the considerations)

thanks
/alessandro

ps: maybe you want to subscribe to the fpga-config-space list at ohwr.org?
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