On Wed, Feb 15, 2012 at 1:50 PM, Erik Van Der Bij <[email protected]> wrote: > In general hardware design these blocks are indeed known as IP cores. > Gateware is more the total of everything and very global. An Ethernet core > sounds more familiar than Ethernet gateware. > LCSD is a nice description of the creative work you guys have going on, so I > have no problem with LCSD. > Erik > >> -----Original Message----- >> From: Sébastien Bourdeauducq >> [mailto:[email protected]] On Behalf Of Sébastien >> Bourdeauducq >> Sent: 15 February 2012 12:38 >> To: Manohar Vanga >> Cc: Javier Serrano; Alan Langman; [email protected]; Milkymist One, >> Milkymist SoC and Flickernoise developers' list; [email protected] >> Subject: Re: Self-Describing Wishbone Bus >> >> Hi, >> >> On 02/13/2012 03:07 PM, Manohar Vanga wrote: >> > Also for the name, I was thinking of yet another horrible acronym: >> > >> > LCSD: Logic Core Self Description (I refuse to put the word IP core >> > into the name anywhere :D). Sounds like LSD... >> >> What about "gateware" instead of "IP core"? It's neutral, descriptive (so >> people unfamiliar with the term can guess what it means), already used by >> some people, and sounds OK: "Ethernet gateware", "acceleration gateware", >> "crypto gateware", "memory controller gateware"... >> >> > I think Alessandro has already replied to this but I add my own too. >> > We want to support devices ranging from constrained to lavish and we >> > were thinking of providing different sized descriptors for differing >> > space availability. What is your opinion of such an approach? >> > >> > We could do something like 64, 32, 16 bit versions of all the parts of >> > the spec (header, id block, device descriptors, child pointers). >> >> Yes, sounds good. >> >> Best, >> Sébastien
Hi. I think there's a bit too much information floating around right now. It seems like my system for handling recursion was well received, and as Manohar presented it at FOSDEM, it seems to be semi-official now. The documentation however has not been updated. I also totally agree with whoever said that most registers are too verbose. My first proposal with only a ID and version might have been a bit too minimalistic, and I agree with Alessandro that we should take care to make it extendable. But it is still important to minimize this, as it will eat up unnecessary resources otherwise. So basically I would like to see a new draft with the recursion system in place and all required registers clearly marked. A list of potential flags and could be good too, so we can have that as a base for further discussion. ...and yes, 16- and 64-bit versions is something that needs to be worked on too. May the best endian-ness win :) -- Olof Kindgren ______________________________________________ ORSoC Website: www.orsoc.se Email: [email protected] ______________________________________________ FPGA, ASIC, DSP - embedded SoC design _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
