With the danger of being noisy, these instructions are subject to
floating point exceptions according to my (perhaps sloppy)
reading of Intel Architecture Instruction Set Extensions
Programming Reference (2012):
(V)ADDPD, (V)ADDPS, (V)ADDSUBPD, (V)ADDSUBPS, (V)CMPPD, (V)CMPPS,
(V)CVTDQ2PS, (V)CVTPD2DQ, (V)CVTPD2PS, (V)CVTPS2DQ, (V)CVTTPD2DQ,
(V)CVTTPS2DQ, (V)DIVPD, (V)DIVPS, (V)DPPD*, (V)DPPS*,
VFMADD132PD, VFMADD213PD, VFMADD231PD, VFMADD132PS, VFMADD213PS,
VFMADD231PS, VFMADDSUB132PD, VFMADDSUB213PD, VFMADDSUB231PD,
VFMADDSUB132PS, VFMADDSUB213PS, VFMADDSUB231PS, VFMSUBADD132PD,
VFMSUBADD213PD, VFMSUBADD231PD, VFMSUBADD132PS, VFMSUBADD213PS,
VFMSUBADD231PS, VFMSUB132PD, VFMSUB213PD, VFMSUB231PD,
VFMSUB132PS, VFMSUB213PS, VFMSUB231PS, VFNMADD132PD,
VFNMADD213PD, VFNMADD231PD, VFNMADD132PS, VFNMADD213PS,
VFNMADD231PS, VFNMSUB132PD, VFNMSUB213PD, VFNMSUB231PD,
VFNMSUB132PS, VFNMSUB213PS, VFNMSUB231PS, (V)HADDPD, (V)HADDPS,
(V)HSUBPD, (V)HSUBPS, (V)MAXPD, (V)MAXPS, (V)MINPD, (V)MINPS,
(V)MULPD, (V)MULPS, (V)ROUNDPS, (V)ROUNDPS, (V)SQRTPD, (V)SQRTPS,
(V)SUBPD, (V)SUBPS
(V)ADDSD, (V)ADDSS, (V)CMPSD, (V)CMPSS, (V)COMISD, (V)COMISS,
(V)CVTPS2PD, (V)CVTSD2SI, (V)CVTSD2SS, (V)CVTSI2SD, (V)CVTSI2SS,
(V)CVTSS2SD, (V)CVTSS2SI, (V)CVTTSD2SI, (V)CVTTSS2SI, (V)DIVSD,
(V)DIVSS, VFMADD132SD, VFMADD213SD, VFMADD231SD, VFMADD132SS,
VFMADD213SS, VFMADD231SS, VFMSUB132SD, VFMSUB213SD, VFMSUB231SD,
VFMSUB132SS, VFMSUB213SS, VFMSUB231SS, VFNMADD132SD,
VFNMADD213SD, VFNMADD231SD, VFNMADD132SS, VFNMADD213SS,
VFNMADD231SS, VFNMSUB132SD, VFNMSUB213SD, VFNMSUB231SD,
VFNMSUB132SS, VFNMSUB213SS, VFNMSUB231SS, (V)MAXSD, (V)MAXSS,
(V)MINSD, (V)MINSS, (V)MULSD, (V)MULSS, (V)ROUNDSD, (V)ROUNDSS,
(V)SQRTSD, (V)SQRTSS, (V)SUBSD, (V)SUBSS, (V)UCOMISD, (V)UCOMISS
VCVTPH2PS, VCVTPS2PH
So I guess Intel floating point exceptions trigger on
computations, but not on moves?
Ola.
