On Wed, Mar 16, 2005 at 01:38:50AM -0000, Robert McGwier wrote:
> I would like to do N, where N is larger than 4, correlators on the FPGA
> in order to do code acquisition for code division multiplexing.  I would
> also
> like to do beam steering experiments on four channels.  All involve
> multiplications and the lower the latency, the better.
> 
> Then the question becomes how MUCH ram is burned in this scheme?  Is it
> onerous?  We are not anywhere near the fill up point in the Cyclone yet
> are we? Can we get a link to this paper instead of just an announcement?

AN 306: Implementing Multipliers in FPGA Devices
http://www.altera.com/literature/an/an306.pdf

Eric


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