Viktor Puš wrote:
>
>>>
>>>
>>>
>> First of all check your VHDL syntax! There are some errors.
>> Create a dummy entity submodule and the instantiation will be documented.
>>
>>
>
>
> There were some errors, thanks. However I have another example, this time
> the VHDL syntax should be correct:
>
> entity top is
> port(
> input : in std_logic;
> output : out std_logic
> );
> end top;
> architecture behav of top is
> component sub
> port (
> release : in std_logic;
> DO : out std_logic_vector(1 downto 0)
> );
> end component;
> begin
> end behav;
>
> If the signal is called "release", then the component sub is not processed
> by Doxygen. I understand from vhdlscanner.l that Doxygen sees "release" as
> VHDL keyword and is therefore confused. But I`ve never seen a VHDL
> compiler that doesn`t let me use the name "release".
>
> Regards,
> Viktor
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Forcing and releasing signals.
But VHDL-2008 allows this in pure VHDL.
<< tb.uut.s >> <= release; -- stop overriding
v <= force in '1'; -- force effective value
v <= force out '0'; -- force driving value
v <= release in; -- release effective value
v <= release out; -- release driving value
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threat landscape has changed and how IT managers can respond. Discussions
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threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
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