> > > Forcing and releasing signals. > > But VHDL-2008 allows this in pure VHDL. > > << tb.uut.s >> <= release; -- stop overriding > > v <= force in '1'; -- force effective value > v <= force out '0'; -- force driving value > > v <= release in; -- release effective value > v <= release out; -- release driving value
Fair enough, I guess it is the VHDL making mess here, adding new reserved words during lifetime. One more question: Can I disable case-sensitivity of Doxygen for VHDL? I have a lot of code using mixed case. entity top is … architecture behav of TOP is This confuses the case-sensitive Doxygen. CASE_SENSE_NAMES option relates only to filenames, not the code. Thanks, Viktor ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ Doxygen-users mailing list Doxygen-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/doxygen-users
