Viktor Puš wrote:
>
>>
>>
>> Forcing and releasing signals.
>>
>> But VHDL-2008 allows this in pure VHDL.
>>
>> << tb.uut.s >> <= release; -- stop overriding
>>
>> v <= force in '1'; -- force effective value
>> v <= force out '0'; -- force driving value
>>
>> v <= release in; -- release effective value
>> v <= release out; -- release driving value
>
> Fair enough, I guess it is the VHDL making mess here, adding new reserved
> words during lifetime.
>
> One more question: Can I disable case-sensitivity of Doxygen for VHDL? I
> have a lot of code using mixed case.
>
> entity top is
> …
> architecture behav of TOP is
>
> This confuses the case-sensitive Doxygen. CASE_SENSE_NAMES option relates
> only to filenames, not the code.
>
> Thanks,
> Viktor
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No, you can't
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