From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
The value the UBWC hardware expects is 13 less than the actual value.
To make it easier to migrate to a common UBWC configuration table,
defer that logic to the data source (which is currently a number of
if-else statements with assignments in case of this driver).
Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +++----
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 ++++++++++++------------------
2 files changed, 15 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index
650e5bac225f372e819130b891f1d020b464f17f..67331a7ee750c0d9eeeead9440e5d08b1a09c878
100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -833,8 +833,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
- BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
- hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
+ hbb = adreno_gpu->ubwc_config.highest_bank_bit;
gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7);
gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1);
@@ -1792,9 +1791,9 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
/* Set the highest bank bit */
if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))
- adreno_gpu->ubwc_config.highest_bank_bit = 15;
+ adreno_gpu->ubwc_config.highest_bank_bit = 2;
else
- adreno_gpu->ubwc_config.highest_bank_bit = 14;
+ adreno_gpu->ubwc_config.highest_bank_bit = 1;
/* a5xx only supports UBWC 1.0, these are not configurable */
adreno_gpu->ubwc_config.macrotile_mode = 0;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index
bf3758f010f4079aa86f9c658b52a70acf10b488..b161b5cd991fc645dfcd69754b82be9691775ffe
100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -592,32 +592,32 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
gpu->ubwc_config.min_acc_len = 0;
gpu->ubwc_config.ubwc_swizzle = 0x6;
gpu->ubwc_config.macrotile_mode = 0;
- gpu->ubwc_config.highest_bank_bit = 15;
+ gpu->ubwc_config.highest_bank_bit = 2;
if (adreno_is_a610(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
gpu->ubwc_config.min_acc_len = 1;
gpu->ubwc_config.ubwc_swizzle = 0x7;
}
if (adreno_is_a618(gpu))
- gpu->ubwc_config.highest_bank_bit = 14;
+ gpu->ubwc_config.highest_bank_bit = 1;
if (adreno_is_a619(gpu))
/* TODO: Should be 14 but causes corruption at e.g. 1920x1200
on DP */
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
if (adreno_is_a619_holi(gpu))
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
if (adreno_is_a621(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
}
if (adreno_is_a623(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 16;
+ gpu->ubwc_config.highest_bank_bit = 3;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
@@ -636,7 +636,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
adreno_is_a730(gpu) ||
adreno_is_a740_family(gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
- gpu->ubwc_config.highest_bank_bit = 16;
+ gpu->ubwc_config.highest_bank_bit = 3;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
@@ -644,7 +644,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
}
if (adreno_is_a663(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
@@ -653,14 +653,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
}
if (adreno_is_7c3(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 14;
+ gpu->ubwc_config.highest_bank_bit = 1;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
if (adreno_is_a702(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 14;
+ gpu->ubwc_config.highest_bank_bit = 1;
gpu->ubwc_config.min_acc_len = 1;
}
}
@@ -668,13 +668,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
- /*
- * We subtract 13 from the highest bank bit (13 is the minimum value
- * allowed by hw) and write the lowest two bits of the remaining value
- * as hbb_lo and the one above it as hbb_hi to the hardware.
- */
- BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
- u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
+ u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
u32 hbb_hi = hbb >> 2;
u32 hbb_lo = hbb & 3;
u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
--
2.49.0
